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TMS570LC4357: Question regarding Silicon Errata MIBSPI#138 and diagnostic MSP16

Max Wittekind
Expert 1875 points
Part Number: TMS570LC4357

Hi experts,

I have a question regarding Errata MIBSPI#138 when executing diagnostic MSP16 "Software test of ECC logic":

To test ECC for 1bit errors we do the following:

  1. Enable Multi-buffer mode by setting bit MSPENA = 1 then enable ECC.
  2. Leave extended buffer mode disabled (EXTENDED_BUF_ENA = 0x5)
  3. configure ECC
  4. Enable ECC memory test by setting bit PTESTEN = 1
  5. Receive RAM access control by setting bit RXRAMACCESS = 1
  6. Enable ECC diagnostic mode by setting bit ECCDIAG_EN = 5
  7. Corrupt ECC by flipping a bit at address (0xFF0E0000U + 0x400U + 0x4U)
  8. read from address 0xFF0E0000U + 0x4U
  9. check for ESM 1.77

Doing it this way works, but the errata mentions the following: "Read operation to ECC address space of MIBSPI RAM in DIAG mode does not return correct ECC value for the first 128 buffers if the Extended Buffer support is implemented but the Extended Mode is disabled for the particular MibSPI instance."

When Setting EXTENDED_BUF_ENA = 0xA (Enable Extended Buffer Mode) the test fails.

Since the description of the errata is rather vague I am I would like to know if MIBSPI#138 should apply to us although the test is working?

Thank you and best regards,
Max

  • 0
    TI__Guru 70211 points

    Hi Max,

    We started working on your issue and will provide you an update ASAP.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 70211 points

    Hi Max,

    I also never verified this errata issue in practical.

    Max Wittekind said:
    Since the description of the errata is rather vague I am I would like to know if MIBSPI#138 should apply to us although the test is working?

    As per my understanding this erratum should be apply.

    Max Wittekind said:
    Doing it this way works

    In your case it might be worked because the flipped bit might be of correct ECC bit only. I mean gives wrong ECC means all bits might not be wrong right? May be any one bit in the 7-bit ECC could be wrong.

    And if you try to do the workaround suggested in the erratum, then remember the below thing:

    If Extended buffer mode is enabled, then address ranges of RAM's will get change because now each RAM will be 256 words.

    TXRAM (Control + Data) Address Range = 0 to 3FFh

    RXRAM (Status + Data) Address Range = 400 to 7FFh

    ECC Address Range = 800 to FFFh

    And also, you should remember below point:

    Even though address range for ECC in extended buffer space is 800 to FFFh but to read the correct ECC values for first 128 buffers we should access from 0xC00 to 0xDFF.

    Please consider this and try to test it again.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1875 points

    Hi Jagadish,

    While implementing the workaround I noticed that I made a wrong assumption in my previous post. We were testing the offsets 0x4 for data and 0x400+0x4 for ECC, which is the TXRAM.

    If the Errata only applies to RXRAM, it would explain, why our implementation works. I would assume ECC-Logik is the same for TXRAM and RXRAM so this test would suffice?

    But I also tested the workaorund for the RXRAM with offsets 0x400 + 0x4 for data and 0xC00 + 0x4 for ECC and it also works (with extendedmode enabled)

    Thank you and best regards,
    Max

  • 0 in reply to Max Wittekind
    TI__Guru 70211 points

    Hi Max,

    Max Wittekind said:

    If the Errata only applies to RXRAM, it would explain, why our implementation works. I would assume ECC-Logik is the same for TXRAM and RXRAM so this test would suffice?

    But I also tested the workaorund for the RXRAM with offsets 0x400 + 0x4 for data and 0xC00 + 0x4 for ECC and it also works (with extendedmode enabled)

    You are right it is for RXRAM only and not for TXRAM.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1875 points

    So testing the TXRam is sufficent, since the ECC Logic is the same as the one for RXRAM right?

  • 0 in reply to Max Wittekind
    TI__Guru 70211 points
    Max Wittekind said:
    So testing the TXRam is sufficent, since the ECC Logic is the same as the one for RXRAM right?

    As you are trying to test MibSPI RAM ECC 1bit error, so it is sufficient to test TXRAM and no need to test RXRAM.

    --
    Thanks & regards,
    Jagadish.