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AM2432: ESL_BOARD_config.h

Guru 10085 points
Part Number: AM2432
Other Parts Discussed in Thread: DP83826E

Hi Support Team,

I have a customer who is considering to implement EtherCAT with AM2432.

Q. Does the following information in the file "ESL_BOARD_config.h" determine the polarity of the signals going into RXLINK, etc.?
     I can't find the relevant part in the code and would appreciate it if you could confirm it for me.

#define ECAT_PHYPOLINVERT_IN (true)
#define ECAT_PHYPOLINVERT_OUT (true)
#define ECAT_PHYUSERXLINK_IN (true)
#define ECAT_PHYUSERXLINK_OUT (true)

Best Regards,
Kanae

  • Hi Kanae,

    Please look at examples\industrial_comms\ethercat_slave_beckhoff_ssc_demo\am243x-lp\tiescsoc.c

    and function:  tiesc_socParamsInit

    Below are the macro in source\industrial_comms\ethercat_slave\icss_fwhal\tiescbsp.h

    #define TIESC_MDIO_RX_LINK_DISABLE  0 //Slow MDIO state m/c based link detection
    #define TIESC_MDIO_RX_LINK_ENABLE   1 //Fast link detect using RXLINK forward from PHY to MDIO MLINK
    #define TIESC_LINK_POL_ACTIVE_LOW       1
    #define TIESC_LINK_POL_ACTIVE_HIGH      0
  • Hi Nilabh,

    Thank you for your reply.

    My customer' comments are here.


    We have confirmed that communication is possible, but there is still a problem. Of the two ports on the IN and OUT sides of the ECAT, the IN side can communicate, but the OUT side cannot.

    To describe the problem in more detail, we have a configuration of a master and two slaves, with the master connected to the IN side of slave ① and slave ② connected to the OUT side.

    Master → Slave ① → Slave ②

    Communication is possible from the master to slave ①, but not to slave ②.
    It appears that data from the master is not reaching slave ② because it is not being successfully passed from the IN side to the OUT side at slave ①.

    Slave ① is set to AM2432.
    The register settings are set as posted above.

    Please let me know what we should check to figure out the cause of this communication failure.


    Best Regards,
    Kanae

  • Could you please provide me below info:

    1. Is this a TI-EVM or a custom board. If this is a custom board, is the schematics as per TI-EVM?

    2.Which SDK version are you using?

    3. Also make sure, Port 0 is connected to master and Port 1 is connected to other slave

  • Hi Nilabh,

    Thank you for your reply.

    1.Custom board.
    It uses a different Phy. Check with the customer if it is ok to disclose the schematic.

    2. Industrial Communications SDK for AM243x (09.00.00.03)

    3. I will check with my customer.

    Best Regards,
    Kanae

  • Hi Nilabh,

    Here are the details from my customer to your questions.

    1. The main changes from TI-EVM to the custom board are as follows
    ICSSG1 -> ICSSG0
    RGMII -> MII

    The schematic around EtherCAT will be shared via private message, although it will be a part of the custom board.

    2. The latest version of the SDK is used.
    Industrial Communications SDK for AM243x (09.00.00.03)

    3. The following connections are made.
    EtherCAT IN ・・・ Master
    EtherCAT OUT ・・・ Other slaves

    Best Regards,
    Kanae

  • Hi Kanae,

    1. The main changes from TI-EVM to the custom board are as follows
    ICSSG1 -> ICSSG0
    RGMII -> MII

    This should not impact much. Can you tell me If the connection is in similar way:

    The schematic around EtherCAT will be shared via private message, although it will be a part of the custom board.

    I will look into it.

    Which master are they using.

  • Hi Nilabh,

    Thank you for your support,

    Here are answers to your questions form customer.


    Nilabh said;
    Can you tell me If the connection is in similar way:

    When evaluating with our custom board, let us explain the circuit diagram that we sent you.
    -Master on EtherCAT IN side
    -Other slaves on the EtherCAT OUT side

    When evaluating with TI-EVM
    -Master on ICSSG1 Port0 side
    -Other slaves on ICSSG1 Port1 side

    Nilabh said;
    Which master are they using.

    The master is TwinCAT3 from Beckhoff.


    Best Regards,
    Kanae

  • Hi Kanae,

    Let me try to reproduce the issue on my end, I will try to get back by next week, Feel free to ping here in case I have not.

  • Hi Nilabh,

    Thank you for your reply.
    I am waiting to know the reproduced results.

    Best Regards,
    Kanae

  • Hi Nilabh,

    It was announced that the SDK will be updated on December 15,
    but I have not yet been able to confirm this from the product website.
    When do you plan to release the updated version?

    Best Regards,
    Kanae

  • Hi Kanae,

    There is a delay in Industrial comms sdk release, due to failure in regression testing. Updated dates are Mid January 2024

  • Hi Nilabh,

    I notified my customer of the delay in the release of the SDK and received the following request.


    We cannot afford to wait until January, so we will continue our investigation without waiting for the release.
    If there is any sample source that has already been confirmed to communicate on the OUT side of EtherCAT,
    can you please provide it to us?


    Best Regards,
    Kanae

  • We cannot afford to wait until January, so we will continue our investigation without waiting for the release.
    If there is any sample source that has already been confirmed to communicate on the OUT side of EtherCAT,
    can you please provide it to us?

    I can understand the urgency, we are also trying on our end. As for example where OUT works with EtherCAT is verified already on ICSSG1 on TI-EVM.

    We are trying on adding ICSSG0 support and we are debugging on our end, will need some time before we conclude the issue, Current status: MDIO__REGS_ALIVE_REG is not set. ETHPHY_DP83826E_verifyIdentifierRegister() is setting the status to fail, hence crashing the application.

    Will be updating the status as soon as we have a break through

  • Hi Nilabh,

    Customer informed us of the current status of the investigation.
    In addition, he requested confirmation of the following register settings.


    Can you please confirm the register setting values that we have set?

    PR1_MII_RT__PR1_MII_RT_CFG_REGS_rxcfg0:0x00000041
    PR1_MII_RT__PR1_MII_RT_CFG_REGS_rxcfg1:0x00000059
    PR1_MII_RT__PR1_MII_RT_CFG_REGS_txcfg0:0x00480401
    PR1_MII_RT__PR1_MII_RT_CFG_REGS_txcfg1: 0x00480701

    Our usage is as follows, as we have already posted you.

    ======================================
    Master → Slave ① → Slave ②
    Slave ① is AM2432.
    Slave ② is connected to the OUT side of Slave ①.
    ICSSG0 is used.
    PORT0 is used for EtherCAT IN side.
    PORT1 is used for EtherCAT OUT side.
    ======================================

    As for the status, when the above register setting values are used,
    it is not that the OUT side cannot communicate at all,
    and when device scan is performed from the master, slave ① and slave ② can be found.
    However, when the state of the found slaves ( ① and ② ) is set to "OP",
    slave ① is set to "OP", but slave ② is set to "IN" instead of "OP".
    However, slave ② does not become "OP" but remains "INIT".
    Slave ① becomes "OP" and PDO/SDO communication is possible.
    On the other hand, slave ② remains "INIT", so PDO/SDO communication is not possible.

    If there is any error in the register setting value, please let us know.


    If you need more information from the customer, please let me know.

    Best Regards,
    Kanae

  • Hi Kanae,

    We were able to successfully run EtherCAT beckoff sub device demo using ICSSG0, we did not see any such issue.

    Which phy is the customer using?

    Also which polling mode are they using - This can be checked in syscfg.

  • Also from the above discussion, I could not figure out whcih example customer is using -

    EthercAT beckoff example or simple ethercat example or something else?

  • Hi Nilabh,

    Thank you for your support.
    The customer verifying this issue has reported the information as follows.


    The problem that the OUT side of EtherCAT cannot communicate has been solved.
    The cause is due to the difference of HW between TI-EVM board and custom board.

    TI-EVM board ・・・ Link status signal output from ECAT PHY side is input to CPU side.

    Custom board ・・・ The above signal is not input to the CPU side.

    The following is an explanation using the schematic diagram provided the other day,
    TI-EVM board ・・・ LED (LINK) signal of PHY is input to CPU.

    Custom board ・・・ LED (SPEED) signal is input to CPU instead of LED (LINK) signal of PHY.

    I modified the custom board and replaced the LED(SPEED) signal with LED(LINK) signal,
    and now the OUT side can also communicate.

    Although the details are still unknown, it seems that the CPU judges the Hi/Low status
    of the PHY link status signal and controls whether the OUT side communicates
    or not according to the Hi/Low status.

    It is thought that the modification enabled the CPU to judge Hi/Low status,
    so that the OUT side communication is now possible.


    If there is a detailed report later, I will post it here as well.

    Best Regards,
    Kanae

  • Hi Nilabh,

    Thank you for your support.
    This issue has been resolved by the customer as described above,
    so I would like to close the case.

    Best regards,
    Kanae