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AM2634-Q1: Does cache invalidation need some time to finish?

Will Gao
Intellectual 2335 points
Part Number: AM2634-Q1

Hi BU experts, 

This question is an urgent case and need your quick and high priority support. 

Customer side found Flash read content sometimes not right (after Flash read, they immediately do CRC check on the content and failed). They tried 3 methods to solve the issue: 1. disable EDMA, no problem anymore; 2. disable cache, also no problem anymore; 3. adding 5us delay after Cache_inv in QSPI_edmaTransfer function, no problem found anymore.

Based on the above observation, I hypothesize that this issue may be caused by cache coherency problem. Since customer immediately used the data after Flash read, and maybe Cache_inv operation needs more time to finished, and before that if CPU read to the buffer it will use the old value in the cache but not the updated one. I compared the buffer result with the Flash content, found that the correct values are aligned at 32-byte which is also the cache line size. 

Need your double confirmation on above analysis and please check internally with the design team that if cache_inv needs some time to be finished and if it is, please also give the needed time. 

Regards, 

Will 

  • 0
    TI__Intellectual 2335 points

    Hi BU, 

    Please feedback this question. Thanks. 

  • 0 in reply to Will Gao
    TI__Intellectual 2335 points

    Hi BU, 

    Please response to the question. 

  • 0 in reply to Will Gao
    TI__Mastermind 26205 points

    Hi Will,

    Apologies for delayed response.

    Our team have tried to reproduce with the read/write for 128KB which works fine. Will customer be able to try with 32 byte cache aligned see if they are able to reproduce the issue. Also will it be possible for customer to share their code to reproduce the issue at our end

    Regards,

    Ankur

  • 0 in reply to Ankur Baranwal
    TI__Intellectual 2335 points

    Hi Ankur, 

    Customer is reading a space with length of 400-byte. Since customer's project has other tasks and they can not share to us. I will let them try Flash read with 32-byte cache-line aligned. 

    Beside this, can you give some analysis on the phenomenon? And also can you please tell if the cache invalidation needs some time to finish and what is the time characteristics? Thanks. 

    Regards, 

    Will 

  • 0 in reply to Will Gao
    TI__Prodigy 140 points

    Hi Will,

    I think the issue here is caused by the EDMA ISR and not due to the cache_inv. I think the read is taking place before the interrupt is generated by edma. that maybe the reason why incorrect values are being read. can you ask them to try using edma without interrupt or let us know how they are implementing the EDMA_ISR function? 

    Regards.

    Shivank

  • 0 in reply to Shivank Sharma
    TI__Intellectual 2335 points

    Hi Shivank, 

    Customer truly uses the interrupt mode, but the ISR is the default function implemented in MCU+ SDK. If this issue is caused by the read is taking place before the EDMA interrupt is generated, I think the wrong data should be in the end range, right? But from the data read out by CPU, the wrong data's distribution is random. 

    Regards, 

    Will 

  • 0 in reply to Will Gao
    TI__Intellectual 2335 points

    The interrupt enabled in the SDK is the aggregated interrupt and the each expected TCC interrupt. TCC interrupt will be issued before the EDMA complete the transfer? It is not reasonable. 

  • 0 in reply to Will Gao
    TI__Intellectual 2335 points

    And the channel is not chained, so I think for one Flash_read, there is only 1 Transfer Request to TPTC and I can see that the codes in SDK is enabling "Transfer Complete Interrupt“  and also "Intermediate Transfer Complete Interrupt". So the TCC interrupt should be issued at the end of the EDMA read. 

    BTW, this issue is not happened each time they read the Flash content and do CRC check. But If this is an interrupt related issue, the issue should always happen.  

  • 0 in reply to Will Gao
    TI__Intellectual 2335 points

    Please check the below wrong result from Flash_read. The 2 buffers are initialized to 0x66666666/0x77777777. The Flash read contents only updates some locations (32-byte aligned). 

  • 0 in reply to Will Gao
    TI__Mastermind 26145 points

    Hi Will,

    Is this issue visible on TI-EVM (i.e. AM263x CC or AM263x LP)  ? Flash read and Cache Invalidate has no correlation whatsoever. If you check the QSPI_edmaTransfer , this function is always started with a Writeback to ensure the Cache is not overwritten and ended with an invalidate so the data in the actual memory should be considered by CPU (not the cache data).

    Do you have a project / test case where customer has reproduced the issue on TI-EVM ? If yes, please share the same. Please keep the tip of software at MCU_PLUS_SDK 09.01 release.

    Best Regards,
    Aakash