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CRC design guideline

Hello Forum,

for estimation purposes I want to know some details about the TMS570 CRC Engine.

In the TRM I've found following informations:

+ 4 Channel MCRC

 

my Questions:

- can the CRC Engine used for saefty critical applications? (is the CRC in the save context of the hardware (RAM, CPU, MPU?)

- Can I use several CRC Engines in parallel?

- Can I select the CRC Polynomial (I Want to use CRC32Q from Aviation) I didn't found an answer in the TRM

- Can I set the Seed (Initial Value) for the CRC Calculation?

- When the CRC works in semi-auto Mode, how many clock cycles can I expect per 100 Bytes of Input Data?

 

Thank you in advance for answers to my basic question!

 

Lorenz

 

  • Hi Lorenz,

    I can answer a few of your questions, but a TI employee might need to answer others.

    1. Beware, there are only 2 MCRC channels, the TRM is incorrect.
    2. I don't know about the save contect of the hardware. 
    3. I have been using both MCRC channels in parallel, fed by different DMA transfers.
    4. You can't select the polynomial as far as I am aware.
    5. You can specify the seed value.
    6. I don't know about exact clock cycle overhead but I found it expensive, and solved this by using DMA

    Hope this gets you started.

    Regards, Tony.

  • Hi Lorenz,

    I am not an expert on this peripheral, but I can tell you:

    - CRC is used heavily by our customers in safety critical applications.  Not sure what you mean about save context, can you please elaborate?

    - You can use multiple CRC channels in parallel

    - CRC polynomial is fixed by hardware to the ISO CRC-64, which is also used for high reliability mass storage.

    - You can set the initial seed

    - CRC can manage 64b of new data per clock cycle; most of your overhead will be in transfer of data to CRC rather than waiting for CRC execution

     

    Regards,

    Karl

  • Thank you for  replies,

     

    you helped me a lot with your Input.

     

    Lorenz