AM2432: PBIST for M4 Core

Hello there,

I have the following questions regarding PBIST for Arm Cortex M4 core in AM2432 Sitara:

1. In the safety manual under reference [SDL_SA_0016] it is mentioned that "PBIST must be run from a different core than is being tested. This is because the test is destructive in nature. For this reason also, after BIST test it is necessary to reset the module." In our application requirement, if we need to run the PBIST on M4 Core and it is assumed that we need to trigger it from R5 core. Please confirm this point and give an example how we can run the PBIST on R5core to test M4core. (this has an impact on our safety concept since we are treating M4 core as the safe core and all R5F cores as non-safe ones - but we could potentially include one R5F core as safety with the appropriate updates to our safety concept)
2. For our application requirements, we would like to know more PBIST timing details i.e. how long the test takes? (Including entry + test completion + exit)
   
   
3. What does SDL_PBIST_INST_INFRA represent? Does it affect M4 Core?
   1. SDL_PBIST_INST_R5F0 Which represents R5 core 0
   2. SDL_PBIST_INST_R5F1 Which represents R5 core 1
   3. SDL_PBIST_INST_MCU Which represents M4 core
   4. SDL_PBIST_INST_INFRA – 
      
      
4. There are two types of PBIST tests one SDL_PBIST_TEST represents normal configuration test and second SDL_PBIST_NEG_TEST represents negative configuration test.
   In our understanding 'SDL_PBIST_TEST' takes care of normal scenario and 'SDL_PBIST_NEG_TEST' injects error and verify that module is able to detect errors in a desired way. Please confirm this point.

Thanks,

Luis