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AM2634-Q1: initial state of GPIO pin

Sung-IL
Mastermind 30940 points
Part Number: AM2634-Q1
Other Parts Discussed in Thread: SYSCONFIG, AM2634

Dear Champs,

Could you please check what is the initial state of GPIO pin in AM2634-Q1?

When my customer checked in their custom board, they found the GPIO pin is high although this pin is open(no HW connection) after boot (UART boot waiting and displaying CPU ID through UART terminal, e.g. no SBL was loaded), but they expect it should be low when they checked datasheet.

Could you please clarify this and below high signal in their GPIO at  boot time before initialization is OK?

Thanks and Best Regards,

SI.

  • 0
    TI__Mastermind 18500 points

    Hi SI, 

    Datasheet default values show the TX/RX/PULL state after reset for each IOMUX pin. Most of those are listed as OFF/OFF/OFF indicating that: 

    • TX disabled
    • RX disabled
    • Pull disabled

    If you program the peripheral to a GPIO pin and set the default pull, you should see the default logic level that you expect. 

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    TI__Mastermind 30940 points

    Hi Randy,

    Thanks for your response.

    So, I expected it should be low before setting GPIO, but it was HIGH signal in customer side.

    is it correct to be HIGH after booting?

    Best Regards, SI

  • 0 in reply to Sung-IL
    TI__Mastermind 18500 points

    Which specific pins on the AM263x device were bring probed? Can you share the SYSCONFIG setup?

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    TI__Mastermind 30940 points

    Hi Randy,

    What I want to know is the exact state of GPIO pin before loading image and sysconfig. They measured it on E4 and D1 pins of AM2634 at UART booting before loading image.

    Thanks and Best Regards,

    SI.

  • +1 in reply to Sung-IL
    TI__Mastermind 18500 points

    Thanks, I think I understand your question now.

    Before ROM execution and before the application image runs, these pins are defined by their "BALL STATE AFTER RESET RX/TX/PULL" and "MUX MODE AFTER RESET" attributes. 

    Pin E4, for example should default to GPIO52 IOMUX mode, with TX/RX/PULLS disabled. Then based on MEM_DIR23 Registers the GPIO52 pin (and the rest of the default GPIO pins) will be set to RX mode. 

    So the voltage on the pin will be entirely determined by any voltage applied to the signal trace from the PCB. 

    Pins that are need by ROM (SOP, UART, QSPI) are configured very quickly after PORZ de-assertion. So during normal start-up there would only be a brief window after 1.2V and 3.3V power-on, but before PORZ where these ROM pins would be in this truly default state. 

    Please let me know if that helps. 

    -Randy