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Dear all,
After setting RESET1(bit 15) in System Exception Control Register (SYSECR)—causing a system software reset—the MCU initialization `FMCECCCHECK_FAIL1` test is failing—which tests for successful correction of a 1-bit error on flash.
Is this behaviour expected?
Thanks for your time and support.
With my best regards,
Luis
Hi Jagadish,
Sorry for the delayed response.
Yes, our code is executing the highlighted line after reset in "fmcECCcheck" function.
In our application code we integrated the HALCOGEN generated code related to MCU initialization as-is (no functional modifications, only minor modifications to enable unit testing).
I tried to insert the HALCOGEN project files but for unknown reasons the upload starts but immediately fails. I just posted at the end of this response the content of the `sys_selftest.c` used as part of our application.
In concrete terms—within the application, at some point after MCU initialization that uses the HALCOGEN generated code—the code used to set the SYSECR bit is below in the following snippet:
`*sysecr_reg = (uint32_t)1U << 15U` with `#define sysecr_reg ((volatile uint32_t *)0xFFFFFFE0U)`
Sorry for the project files inconvenience. Is the information provided sufficient to help you answer my question?
Thanks for your time.
Best regards,
Luis
/** @file sys_selftest.c
* @brief Selftest Source File
* @version 04.07.01
* This file contains:
* - Selftest API's
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_selftest.h"
#include "sys_core.h"
#include "sys_pmu.h"
#ifdef CEEDLING_TEST
#include "reg_fmtm.h"
#endif
/** @fn void selftestFailNotification(uint32 flag)
* @brief Self test fail service routine
*
* This function is called if there is a self test fail with appropriate flag
*/
#pragma WEAK(selftestFailNotification)
void selftestFailNotification(uint32 flag)
{
/* USER CODE BEGIN (1) */
/* USER CODE END */
}
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @fn void ccmSelfCheck(void)
* @brief CCM module self check Driver
*
* This function self checks the CCM module.
*/
/* SourceId : SELFTEST_SourceId_001 */
/* DesignId : SELFTEST_DesignId_001 */
/* Requirements : HL_SR395 */
void ccmSelfCheck(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Run a diagnostic check on the CCM-R4F module */
/* This step ensures that the CCM-R4F can actually indicate an error */
/* Configure CCM in self-test mode */
CCMKEYR = 0x6U;
/* Wait for CCM self-test to complete */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((CCMSR & 0x100U) != 0x100U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (4) */
/* USER CODE END */
/* Check if there was an error during the self-test */
if ((CCMSR & 0x1U) == 0x1U)
{
/* STE is set */
selftestFailNotification(CCMSELFCHECK_FAIL1);
}
else
{
/* Check CCM-R4 self-test error flag by itself (without compare error) */
if ((esmREG->SR1[0U] & 0x80000000U) == 0x80000000U)
{
/* ESM flag is not set */
selftestFailNotification(CCMSELFCHECK_FAIL2);
}
else
{
/* Configure CCM in error-forcing mode */
CCMKEYR = 0x9U;
/* Wait till error-forcing is completed. */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while (CCMKEYR != 0U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* check if compare error flag is set */
if ((esmREG->SR1[1U] & 0x4U) != 0x4U)
{
/* ESM flag is not set */
selftestFailNotification(CCMSELFCHECK_FAIL3);
}
else
{
/* Check FIQIVEC to ESM High Interrupt flag is set */
if((vimREG->FIQINDEX & 0x000000FFU) != 1U)
{
/* ESM High Interrupt flag is not set in VIM*/
selftestFailNotification(CCMSELFCHECK_FAIL4);
}
/* clear ESM group2 channel 2 flag */
esmREG->SR1[1U] = 0x4U;
/* clear ESM group2 shadow status flag */
esmREG->SSR2 = 0x4U;
/* ESM self-test error needs to also be cleared */
esmREG->SR1[0U] = 0x80000000U;
/* The nERROR pin will become inactive once the LTC counter expires */
esmREG->EKR = 0x5U;
/* Configure CCM in selftest error-forcing mode */
CCMKEYR = 0xFU;
/* Wait till selftest error-forcing is completed. */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while (CCMKEYR != 0U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
if((esmREG->SR1[0U] & 0x80000000U) != 0x80000000U)
{
/* ESM flag not set */
selftestFailNotification(CCMSELFCHECK_FAIL2);
}
else
{
/* clear ESM flag */
esmREG->SR1[0U] = 0x80000000U;
}
}
}
}
}
/* USER CODE BEGIN (5) */
/* USER CODE END */
/** @fn void memoryInit(uint32 ram)
* @brief Memory Initialization Driver
*
* This function is called to perform Memory initialization of selected RAM's.
*/
/* SourceId : SELFTEST_SourceId_002 */
/* DesignId : SELFTEST_DesignId_004 */
/* Requirements : HL_SR396 */
void memoryInit(uint32 ram)
{
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Enable Memory Hardware Initialization */
systemREG1->MINITGCR = 0xAU;
/* Enable Memory Hardware Initialization for selected RAM's */
systemREG1->MSINENA = ram;
/* Wait until Memory Hardware Initialization complete */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* Disable Memory Hardware Initialization */
systemREG1->MINITGCR = 0x5U;
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
/** @fn void stcSelfCheck(void)
* @brief STC module self check Driver
*
* This function is called to perform STC module self check.
*/
/* SourceId : SELFTEST_SourceId_003 */
/* DesignId : SELFTEST_DesignId_002 */
/* Requirements : HL_SR397 */
void stcSelfCheck(void)
{
/* USER CODE BEGIN (8) */
/* USER CODE END */
volatile uint32 i = 0U;
/* Run a diagnostic check on the CPU self-test controller */
/* First set up the STC clock divider as STC is only supported up to 90MHz */
/* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */
systemREG2->STCCLKDIV = 0x01000000U;
/* Select one test interval, restart self-test next time, 0x00010001 */
stcREG->STCGCR0 = 0x00010001U;
/* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
stcREG->STCSCSCR = 0x1AU;
/* Maximum time-out period */
stcREG->STCTPR = 0xFFFFFFFFU;
/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }
/* Enable self-test */
stcREG->STCGCR1 = 0xAU;
/* USER CODE BEGIN (9) */
/* USER CODE END */
/* Idle the CPU so that the self-test can start */
_gotoCPUIdle_();
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
* @brief CPU self test Driver
* @param[in] no_of_intervals - Number of Test Intervals to be
* @param[in] max_timeout - Maximum Timeout to complete selected test Intervals
* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped.
*
* This function is called to perform CPU self test using STC module.
*/
/* SourceId : SELFTEST_SourceId_004 */
/* DesignId : SELFTEST_DesignId_003 */
/* Requirements : HL_SR398 */
void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
{
volatile uint32 i = 0U;
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Run specified no of test intervals starting from interval 0 */
/* Start test from interval 0 or continue the test. */
stcREG->STCGCR0 = no_of_intervals << 16U;
if(restart_test)
{
stcREG->STCGCR0 |= 0x00000001U;
}
/* Configure Maximum time-out period */
stcREG->STCTPR = max_timeout;
/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }
/* Enable self-test */
stcREG->STCGCR1 = 0xAU;
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Idle the CPU so that the self-test can start */
_gotoCPUIdle_();
}
/** @fn void pbistSelfCheck(void)
* @brief PBIST self test Driver
*
* This function is called to perform PBIST self test.
*
* @note This Function uses register's which are not exposed to users through
* TRM , to run custom algorithm to make PBIST Fail. Users can use this function as Black box.
*
*/
/* SourceId : SELFTEST_SourceId_005 */
/* DesignId : SELFTEST_DesignId_005 */
/* Requirements : HL_SR399 */
void pbistSelfCheck(void)
{
volatile uint32 i = 0U;
uint32 PBIST_wait_done_loop = 0U;
/* USER CODE BEGIN (13) */
/* USER CODE END */
/* Run a diagnostic check on the memory self-test controller */
/* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;
/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000105U;
/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;
/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000010AU;
/* Clear PBIST Done */
systemREG1->MSTCGSTAT = 0x1U;
/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;
/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x3U;
/* CPU control of PBIST */
pbistREG->DLR = 0x10U;
/* Custom always fail algo, this will not use the ROM and just set a fail */
pbistREG->RAMT = 0x00002000U;
#ifdef CEEDLING_TEST
pbistREG->rsvd0[0x000 >> 2] = 0x4C000001U;
pbistREG->rsvd0[0x040 >> 2] = 0x00000075U;
pbistREG->rsvd0[0x004 >> 2] = 0x4C000002U;
pbistREG->rsvd0[0x044 >> 2] = 0x00000075U;
pbistREG->rsvd0[0x008 >> 2] = 0x4C000003U;
pbistREG->rsvd0[0x048 >> 2] = 0x00000075U;
pbistREG->rsvd0[0x00C >> 2] = 0x4C000004U;
pbistREG->rsvd0[0x04C >> 2] = 0x00000075U;
pbistREG->rsvd0[0x010 >> 2] = 0x4C000005U;
pbistREG->rsvd0[0x050 >> 2] = 0x00000075U;
pbistREG->rsvd0[0x014 >> 2] = 0x4C000006U;
pbistREG->rsvd0[0x054 >> 2] = 0x00000075U;
pbistREG->rsvd0[0x018 >> 2] = 0x00000000U;
pbistREG->rsvd0[0x058 >> 2] = 0x00000001U;
#else
*(volatile uint32 *)0xFFFFE400U = 0x4C000001U;
*(volatile uint32 *)0xFFFFE440U = 0x00000075U;
*(volatile uint32 *)0xFFFFE404U = 0x4C000002U;
*(volatile uint32 *)0xFFFFE444U = 0x00000075U;
*(volatile uint32 *)0xFFFFE408U = 0x4C000003U;
*(volatile uint32 *)0xFFFFE448U = 0x00000075U;
*(volatile uint32 *)0xFFFFE40CU = 0x4C000004U;
*(volatile uint32 *)0xFFFFE44CU = 0x00000075U;
*(volatile uint32 *)0xFFFFE410U = 0x4C000005U;
*(volatile uint32 *)0xFFFFE450U = 0x00000075U;
*(volatile uint32 *)0xFFFFE414U = 0x4C000006U;
*(volatile uint32 *)0xFFFFE454U = 0x00000075U;
*(volatile uint32 *)0xFFFFE418U = 0x00000000U;
*(volatile uint32 *)0xFFFFE458U = 0x00000001U;
#endif
/* PBIST_RUN */
pbistREG->rsvd1[1U] = 1U;
/* wait until memory self-test done is indicated */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U)
{
PBIST_wait_done_loop++;
}/* Wait */
/* Check for the failure */
if ((pbistREG->FSRF0 & 0x1U) != 0x1U)
{
/* No failure was indicated even if the always fail algorithm was run*/
selftestFailNotification(PBISTSELFCHECK_FAIL1);
/* USER CODE BEGIN (15) */
/* USER CODE END */
}
else
{
/* Check that the algorithm executed in the expected amount of time. */
/* This time is dependent on the ROMCLKDIV selected above */
if (PBIST_wait_done_loop >= 2U)
{
selftestFailNotification(PBISTSELFCHECK_FAIL2);
}
/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;
/* Disable PBIST */
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
}
/** @fn void pbistRun(uint32 raminfoL, uint32 algomask)
* @brief CPU self test Driver
* @param[in] raminfoL - Select the list of RAM to be tested.
* @param[in] algomask - Select the list of Algorithm to be run.
*
* This function performs Memory Built-in Self test using PBIST module.
*/
/* SourceId : SELFTEST_SourceId_006 */
/* DesignId : SELFTEST_DesignId_006 */
/* Requirements : HL_SR400 */
void pbistRun(uint32 raminfoL, uint32 algomask)
{
volatile uint32 i = 0U;
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000105U;
/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;
/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;
/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000010AU;
/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x3U;
/* Select all algorithms to be tested */
pbistREG->ALGO = algomask;
/* Select RAM groups */
pbistREG->RINFOL = raminfoL;
/* Select all RAM groups */
pbistREG->RINFOU = 0x00000000U;
/* ROM contents will not override RINFOx settings */
pbistREG->OVER = 0x0U;
/* Algorithm code is loaded from ROM */
pbistREG->ROM = 0x3U;
/* Start PBIST */
pbistREG->DLR = 0x14U;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
/** @fn void pbistStop(void)
* @brief Routine to stop PBIST test enabled.
*
* This function is called to stop PBIST after test is performed.
*/
/* SourceId : SELFTEST_SourceId_007 */
/* DesignId : SELFTEST_DesignId_007 */
/* Requirements : HL_SR523 */
void pbistStop(void)
{
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* disable pbist clocks and ROM clock */
pbistREG->PACT = 0x0U;
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
/** @fn boolean pbistIsTestCompleted(void)
* @brief Checks to see if the PBIST test is completed.
* @return 1 if PBIST test completed, otherwise 0.
*
* Checks to see if the PBIST test is completed.
*/
/* SourceId : SELFTEST_SourceId_008 */
/* DesignId : SELFTEST_DesignId_008 */
/* Requirements : HL_SR401 */
boolean pbistIsTestCompleted(void)
{
/* USER CODE BEGIN (22) */
/* USER CODE END */
return ((systemREG1->MSTCGSTAT & 0x1U) != 0U);
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/** @fn boolean pbistIsTestPassed(void)
* @brief Checks to see if the PBIST test is completed successfully.
* @return 1 if PBIST test passed, otherwise 0.
*
* Checks to see if the PBIST test is completed successfully.
*/
/* SourceId : SELFTEST_SourceId_009 */
/* DesignId : SELFTEST_DesignId_009 */
/* Requirements : HL_SR401 */
boolean pbistIsTestPassed(void)
{
/* USER CODE BEGIN (24) */
/* USER CODE END */
boolean status;
if (pbistREG->FSRF0 == 0U)
{
status = TRUE;
}
else
{
status = FALSE;
}
/* USER CODE BEGIN (25) */
/* USER CODE END */
return status;
}
/** @fn boolean pbistPortTestStatus(uint32 port)
* @brief Checks to see if the PBIST Port test is completed successfully.
* @param[in] port - Select the port to get the status.
* @return 1 if PBIST Port test completed successfully, otherwise 0.
*
* Checks to see if the selected PBIST Port test is completed successfully.
*/
/* SourceId : SELFTEST_SourceId_010 */
/* DesignId : SELFTEST_DesignId_010 */
/* Requirements : HL_SR401 */
boolean pbistPortTestStatus(uint32 port)
{
boolean status;
/* USER CODE BEGIN (26) */
/* USER CODE END */
if(port == (uint32)PBIST_PORT0)
{
status = (pbistREG->FSRF0 == 0U);
}
else
{
/* Invalid Input */
status = FALSE;
}
return status;
}
/** @fn uint32 efcCheck(void)
* @brief EFUSE module self check Driver
* @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed
* 1 if no error was detected during autoload but Stuck At Zero Test failed
* 2 if there was a single-bit error detected during autoload
* 3 if some other error occurred during autoload
*
* This function self checks the EFUSE module.
*/
/* SourceId : SELFTEST_SourceId_011 */
/* DesignId : SELFTEST_DesignId_012 */
/* Requirements : HL_SR402 */
uint32 efcCheck(void)
{
uint32 efcStatus = 0U;
uint32 status;
/* USER CODE BEGIN (27) */
/* USER CODE END */
/* read the EFC Error Status Register */
efcStatus = efcREG->ERROR;
/* USER CODE BEGIN (28) */
/* USER CODE END */
if (efcStatus == 0x0U)
{
/* run stuck-at-zero test and check if it passed */
if (efcStuckZeroTest()== TRUE)
{
/* start EFC ECC logic self-test */
efcSelfTest();
status = 0U;
}
else
{
/* EFC output is stuck-at-zero, device operation unreliable */
selftestFailNotification(EFCCHECK_FAIL1);
status = 1U;
}
}
/* EFC Error Register is not zero */
else
{
/* one-bit error detected during autoload */
if (efcStatus == 0x15U)
{
/* start EFC ECC logic self-test */
efcSelfTest();
status = 2U;
}
else
{
/* Some other EFC error was detected */
selftestFailNotification(EFCCHECK_FAIL1);
status = 3U;
}
}
return status;
}
/** @fn boolean efcStuckZeroTest(void)
* @brief Checks to see if the EFUSE Stuck at zero test is completed successfully.
* @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
*
* Checks to see if the EFUSE Stuck at zero test is completed successfully.
*/
/* SourceId : SELFTEST_SourceId_012 */
/* DesignId : SELFTEST_DesignId_014 */
/* Requirements : HL_SR402 */
boolean efcStuckZeroTest(void)
{
/* USER CODE BEGIN (29) */
/* USER CODE END */
uint32 ESM_ESTATUS4, ESM_ESTATUS1;
boolean result = FALSE;
uint32 error_checks = EFC_INSTRUCTION_INFO_EN |
EFC_INSTRUCTION_ERROR_EN |
EFC_AUTOLOAD_ERROR_EN |
EFC_SELF_TEST_ERROR_EN ;
/* configure the output enable for auto load error , instruction info,
instruction error, and self test error using boundary register
and drive values one across all the errors */
efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks);
/* Read from the pin register. This register holds the current values
of above errors. This value should be 0x5c00.If not at least one of
the above errors is stuck at 0. */
if ((efcREG->PINS & 0x5C00U) == 0x5C00U)
{
ESM_ESTATUS4 = esmREG->SR4[0U];
ESM_ESTATUS1 = esmREG->SR1[2U];
/* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
if (((ESM_ESTATUS4 & 0x200U) == 0x200U) && ((ESM_ESTATUS1 & 0x2U) == 0x2U))
{
/* stuck-at-zero test passed */
result = TRUE;
}
}
/* put the pins back low */
efcREG->BOUNDARY = OUTPUT_ENABLE;
/* clear group1 flag */
esmREG->SR4[0U] = 0x200U;
/* clear group3 flag */
esmREG->SR1[2U] = 0x2U;
/* The nERROR pin will become inactive once the LTC counter expires */
esmREG->EKR = 0x5U;
return result;
}
/** @fn void efcSelfTest(void)
* @brief EFUSE module self check Driver
*
* This function self checks the EFSUE module.
*/
/* SourceId : SELFTEST_SourceId_013 */
/* DesignId : SELFTEST_DesignId_013 */
/* Requirements : HL_SR402 */
void efcSelfTest(void)
{
/* USER CODE BEGIN (30) */
/* USER CODE END */
/* configure self-test cycles */
efcREG->SELF_TEST_CYCLES = 0x258U;
/* configure self-test signature */
efcREG->SELF_TEST_SIGN = 0x5362F97FU;
/* configure boundary register to start ECC self-test */
efcREG->BOUNDARY = 0x0000200FU;
}
/** @fn boolean checkefcSelfTest(void)
* @brief EFUSE module self check Driver
* @return Returns TRUE if EFC Selftest was a PASS, else FALSE
*
* This function returns the status of efcSelfTest.
* Note: This function can be called only after calling efcSelfTest
*/
/* SourceId : SELFTEST_SourceId_014 */
/* DesignId : SELFTEST_DesignId_015 */
/* Requirements : HL_SR403 */
boolean checkefcSelfTest(void)
{
/* USER CODE BEGIN (31) */
/* USER CODE END */
boolean result = FALSE;
uint32 EFC_PINS, EFC_ERROR;
uint32 esmCh40Stat, esmCh41Stat = 0U;
/* wait until EFC self-test is done */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((efcREG->PINS & EFC_SELF_TEST_DONE) == 0U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* check if EFC self-test error occurred */
EFC_PINS = efcREG->PINS;
EFC_ERROR = efcREG->ERROR;
if(((EFC_PINS & EFC_SELF_TEST_ERROR) == 0U) && ((EFC_ERROR & 0x1FU) == 0U))
{
/* check if EFC self-test error is set */
esmCh40Stat = esmREG->SR4[0U] & 0x100U;
esmCh41Stat = esmREG->SR4[0U] & 0x200U;
if ((esmCh40Stat == 0U) && (esmCh41Stat == 0U))
{
result = TRUE;
}
}
return result;
}
/** @fn void fmcBus2Check(void)
* @brief Self Check Flash Bus2 Interface
*
* This function self checks Flash Bus2 Interface
*/
/* SourceId : SELFTEST_SourceId_015 */
/* DesignId : SELFTEST_DesignId_016 */
/* Requirements : HL_SR404, HL_SR405 */
void fmcBus2Check(void)
{
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* enable ECC logic inside FMC */
flashWREG->FEDACCTRL1 = 0x000A060AU;
if ((esmREG->SR1[0U] & 0x40U) == 0x40U)
{
/* a 1-bit error was detected during flash OTP read by flash module
run a self-check on ECC logic inside FMC */
/* clear ESM group1 channel 6 flag */
esmREG->SR1[0U] = 0x40U;
fmcECCcheck();
}
/* no 2-bit or 1-bit error detected during power-up */
else
{
fmcECCcheck();
}
/* USER CODE BEGIN (33) */
/* USER CODE END */
}
/** @fn void fmcECCcheck(void)
* @brief Check Flash ECC Single Bit and multi Bit errors detection logic.
*
* This function Checks Flash ECC Single Bit and multi Bit errors detection logic.
*/
/* SourceId : SELFTEST_SourceId_016 */
/* DesignId : SELFTEST_DesignId_017 */
/* Requirements : HL_SR404, HL_SR405 */
void fmcECCcheck(void)
{
volatile uint32 otpread;
volatile uint32 temp;
/* USER CODE BEGIN (34) */
/* USER CODE END */
/* read location with deliberate 1-bit error */
otpread = flash1bitError;
if ((esmREG->SR1[0U] & 0x40U) == 0x40U)
{
/* 1-bit failure was indicated and corrected */
flashWREG->FEDACSTATUS = 0x00010006U;
/* clear ESM group1 channel 6 flag */
esmREG->SR1[0U] = 0x40U;
/* read location with deliberate 2-bit error */
otpread = flash2bitError;
if ((esmREG->SR1[2U] & 0x80U) == 0x80U)
{
/* 2-bit failure was detected correctly */
temp = flashWREG->FUNCERRADD;
flashWREG->FEDACSTATUS = 0x00020100U;
/* clear ESM group3 channel 7 */
esmREG->SR1[2U] = 0x80U;
/* The nERROR pin will become inactive once the LTC counter expires */
esmREG->EKR = 0x5U;
}
else
{
/* ECC logic inside FMC cannot detect 2-bit error */
selftestFailNotification(FMCECCCHECK_FAIL1);
}
}
else
{
/* ECC logic inside FMC cannot detect 1-bit error */
selftestFailNotification(FMCECCCHECK_FAIL1);
}
/* USER CODE BEGIN (35) */
/* USER CODE END */
}
/** @fn void checkFlashECC(void)
* @brief Check Flash ECC error detection logic.
*
* This function checks Flash ECC error detection logic.
*/
/* SourceId : SELFTEST_SourceId_019 */
/* DesignId : SELFTEST_DesignId_020 */
/* Requirements : HL_SR405 */
void checkFlashECC(void)
{
/* Routine to check operation of ECC logic inside CPU for accesses to program flash */
volatile uint32 flashread = 0U;
/* USER CODE BEGIN (40) */
/* USER CODE END */
/* Flash Module ECC Response enabled */
flashWREG->FEDACCTRL1 = 0x000A060AU;
/* Enable diagnostic mode and select diag mode 7 */
flashWREG->FDIAGCTRL = 0x00050007U;
/* Select ECC diagnostic mode, single-bit to be corrupted */
flashWREG->FPAROVR = 0x00005A01U;
/* Set the trigger for the diagnostic mode */
flashWREG->FDIAGCTRL |= 0x01000000U;
/* read a flash location from the mirrored memory map */
flashread = flashBadECC1;
/* disable diagnostic mode */
flashWREG->FDIAGCTRL = 0x000A0007U;
/* this will have caused a single-bit error to be generated and corrected by CPU */
/* single-bit error not captured in flash module */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if ((flashWREG->FEDACSTATUS & 0x2U) == 0U)
{
selftestFailNotification(CHECKFLASHECC_FAIL1);
}
else
{
/* clear single-bit error flag */
flashWREG->FEDACSTATUS = 0x2U;
/* clear ESM flag */
esmREG->SR1[0U] = 0x40U;
/* Enable diagnostic mode and select diag mode 7 */
flashWREG->FDIAGCTRL = 0x00050007U;
/* Select ECC diagnostic mode, two bits of ECC to be corrupted */
flashWREG->FPAROVR = 0x00005A03U;
/* Set the trigger for the diagnostic mode */
flashWREG->FDIAGCTRL |= 0x01000000U;
/* read from flash location from mirrored memory map this will cause a data abort */
flashread = flashBadECC2;
/* Read FUNCERRADD register */
flashread = flashWREG->FUNCERRADD;
/* disable diagnostic mode */
flashWREG->FDIAGCTRL = 0x000A0007U;
}
/* USER CODE BEGIN (41) */
/* USER CODE END */
}
/** @fn void custom_dabort(void)
* @brief Custom Data abort routine for the application.
*
* Custom Data abort routine for the application.
*/
void custom_dabort(void)
{
/* Need custom data abort handler here.
* This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.
*/
/* USER CODE BEGIN (42) */
/* USER CODE END */
}
/** @fn void stcSelfCheckFail(void)
* @brief STC Self test check fail service routine
*
* This function is called if STC Self test check fail.
*/
void stcSelfCheckFail(void)
{
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* CPU self-test controller's own self-test failed.
* It is not possible to verify that STC is capable of indicating a CPU self-test error.
* It is not recommended to continue operation.
*/
/* User can add small piece of code to take system to Safe state using user code section.
* Note: Just removing the for(;;) will take the system to unknown state under ST failure,
* since it is not handled by HALCoGen driver */
/* USER CODE BEGIN (44) */
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (45) */
/* USER CODE END */
}
/** @fn void cpuSelfTestFail(void)
* @brief CPU Self test check fail service routine
*
* This function is called if CPU Self test check fail.
*/
void cpuSelfTestFail(void)
{
/* USER CODE BEGIN (46) */
/* USER CODE END */
/* CPU self-test has failed.
* CPU operation is not reliable.
*/
/* USER CODE BEGIN (47) */
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (48) */
/* USER CODE END */
}
/** @fn void vimParityCheck(void)
* @brief Routine to check VIM RAM parity error detection and signaling mechanism
*
* Routine to check VIM RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_020 */
/* DesignId : SELFTEST_DesignId_021 */
/* Requirements : HL_SR385 */
void vimParityCheck(void)
{
volatile uint32 vimramread = 0U;
uint32 vimparctl_bk = VIM_PARCTL;
/* USER CODE BEGIN (49) */
/* USER CODE END */
/* Enable parity checking and parity test mode */
VIM_PARCTL = 0x0000010AU;
/* flip a bit in the VIM RAM parity location */
VIMRAMPARLOC ^= 0x1U;
/* disable parity test mode */
VIM_PARCTL = 0x0000000AU;
/* cause parity error */
vimramread = VIMRAMLOC;
/* check if ESM group1 channel 15 is flagged */
if ((esmREG->SR1[0U] & 0x8000U) ==0U)
{
/* VIM RAM parity error was not flagged to ESM. */
selftestFailNotification(VIMPARITYCHECK_FAIL1);
}
else
{
/* clear VIM RAM parity error flag in VIM */
VIM_PARFLG = 0x1U;
/* clear ESM group1 channel 15 flag */
esmREG->SR1[0U] = 0x8000U;
/* Enable parity checking and parity test mode */
VIM_PARCTL = 0x0000010AU;
/* Revert back to correct data, flip bit 0 of the parity location */
VIMRAMPARLOC ^= 0x1U;
}
/* Restore Parity Control register */
VIM_PARCTL = vimparctl_bk;
/* USER CODE BEGIN (50) */
/* USER CODE END */
}
/** @fn void het1ParityCheck(void)
* @brief Routine to check HET1 RAM parity error detection and signaling mechanism
*
* Routine to check HET1 RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_022 */
/* DesignId : SELFTEST_DesignId_024 */
/* Requirements : HL_SR389 */
void het1ParityCheck(void)
{
volatile uint32 nhetread = 0U;
uint32 hetpcr_bk = hetREG1->PCR;
/* USER CODE BEGIN (53) */
/* USER CODE END */
/* Set TEST mode and enable parity checking */
hetREG1->PCR = 0x0000010AU;
/* flip parity bit */
NHET1RAMPARLOC ^= 0x1U;
/* Disable TEST mode */
hetREG1->PCR = 0x0000000AU;
/* read to cause parity error */
nhetread = NHET1RAMLOC;
/* check if ESM group1 channel 7 is flagged */
if ((esmREG->SR1[0U] & 0x80U) ==0U)
{
/* NHET1 RAM parity error was not flagged to ESM. */
selftestFailNotification(HET1PARITYCHECK_FAIL1);
}
else
{
/* clear ESM group1 channel 7 flag */
esmREG->SR1[0U] = 0x80U;
/* Set TEST mode and enable parity checking */
hetREG1->PCR = 0x0000010AU;
/* Revert back to correct data, flip bit 0 of the parity location */
NHET1RAMPARLOC ^= 0x1U;
}
/* Restore Parity comtrol register */
hetREG1->PCR = hetpcr_bk;
/* USER CODE BEGIN (54) */
/* USER CODE END */
}
/** @fn void adc1ParityCheck(void)
* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism
*
* Routine to check ADC1 RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_026 */
/* DesignId : SELFTEST_DesignId_023 */
/* Requirements : HL_SR387 */
void adc1ParityCheck(void)
{
volatile uint32 adcramread = 0U;
uint32 adcparcr_bk = adcREG1->PARCR;
/* USER CODE BEGIN (61) */
/* USER CODE END */
/* Set the TEST bit in the PARCR and enable parity checking */
adcREG1->PARCR = 0x10AU;
/* Invert the parity bits inside the ADC1 RAM's first location */
adcPARRAM1 = ~(adcPARRAM1);
/* clear the TEST bit */
adcREG1->PARCR = 0x00AU;
/* This read is expected to trigger a parity error */
adcramread = adcRAM1;
/* Check for ESM group1 channel 19 to be flagged */
if ((esmREG->SR1[0U] & 0x80000U) ==0U)
{
/* no ADC1 RAM parity error was flagged to ESM */
selftestFailNotification(ADC1PARITYCHECK_FAIL1);
}
else
{
/* clear ADC1 RAM parity error flag */
esmREG->SR1[0U] = 0x80000U;
/* Set the TEST bit in the PARCR and enable parity checking */
adcREG1->PARCR = 0x10AU;
/* Revert back the parity bits to correct data */
adcPARRAM1 = ~(adcPARRAM1);
}
/* Restore parity control register */
adcREG1->PARCR = adcparcr_bk;
/* USER CODE BEGIN (62) */
/* USER CODE END */
}
/** @fn void adc2ParityCheck(void)
* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism
*
* Routine to check ADC2 RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_027 */
/* DesignId : SELFTEST_DesignId_023 */
/* Requirements : HL_SR387 */
void adc2ParityCheck(void)
{
volatile uint32 adcramread = 0U;
uint32 adcparcr_bk = adcREG2->PARCR;
/* USER CODE BEGIN (63) */
/* USER CODE END */
/* Set the TEST bit in the PARCR and enable parity checking */
adcREG2->PARCR = 0x10AU;
/* Invert the parity bits inside the ADC2 RAM's first location */
adcPARRAM2 = ~(adcPARRAM2);
/* clear the TEST bit */
adcREG2->PARCR = 0x00AU;
/* This read is expected to trigger a parity error */
adcramread = adcRAM2;
/* Check for ESM group1 channel 1 to be flagged */
if ((esmREG->SR1[0U] & 0x2U) == 0U)
{
/* no ADC2 RAM parity error was flagged to ESM */
selftestFailNotification(ADC2PARITYCHECK_FAIL1);
}
else
{
/* clear ADC2 RAM parity error flag */
esmREG->SR1[0U] = 0x2U;
/* Set the TEST bit in the PARCR and enable parity checking */
adcREG2->PARCR = 0x10AU;
/* Revert back the parity bits to correct data */
adcPARRAM2 = ~(adcPARRAM2);
}
/* Restore parity control register*/
adcREG2->PARCR = adcparcr_bk;
/* USER CODE BEGIN (64) */
/* USER CODE END */
}
/** @fn void can1ParityCheck(void)
* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism
*
* Routine to check CAN1 RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_028 */
/* DesignId : SELFTEST_DesignId_026 */
/* Requirements : HL_SR393 */
void can1ParityCheck(void)
{
volatile uint32 canread = 0U;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
uint32 canctl_bk = canREG1->CTL;
/* USER CODE BEGIN (65) */
/* USER CODE END */
/* Disable parity, init mode, TEST mode */
canREG1->CTL = 0x00001481U;
/* Enable RAM Direct Access mode */
canREG1->TEST = 0x00000200U;
/* flip the parity bit */
canPARRAM1 ^= 0x00001000U;
/* Enable parity, disable init, still TEST mode */
canREG1->CTL = 0x00002880U;
/* Read location with parity error */
canread = canRAM1;
/* check if ESM group1 channel 21 is flagged */
if ((esmREG->SR1[0U] & 0x00200000U) == 0U)
{
/* No DCAN1 RAM parity error was flagged to ESM */
selftestFailNotification(CAN1PARITYCHECK_FAIL1);
}
else
{
/* clear ESM group1 channel 21 flag */
esmREG->SR1[0U] = 0x00200000U;
/* Disable parity, init mode, TEST mode */
canREG1->CTL = 0x00001481U;
/* Revert back to correct data, flip bit 0 of the parity location */
canPARRAM1 ^= 0x00001000U;
}
/* Disable RAM Direct Access mode */
canREG1->TEST = 0x00000000U;
/* Restore CTL register */
canREG1->CTL = canctl_bk;
/* Read Error and Status register to clear Parity Error bit */
canread = canREG1->ES;
/* USER CODE BEGIN (66) */
/* USER CODE END */
}
/** @fn void can2ParityCheck(void)
* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism
*
* Routine to check CAN2 RAM parity error detection and signaling mechanism
*/
/* SourceId : SELFTEST_SourceId_029 */
/* DesignId : SELFTEST_DesignId_026 */
/* Requirements : HL_SR393 */
void can2ParityCheck(void)
{
volatile uint32 canread = 0U;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
uint32 canctl_bk = canREG2->CTL;
/* USER CODE BEGIN (67) */
/* USER CODE END */
/* Disable parity, init mode, TEST mode */
canREG2->CTL = 0x00001481U;
/* Enable RAM Direct Access mode */
canREG2->TEST = 0x00000200U;
/* flip the parity bit */
canPARRAM2 ^= 0x00001000U;
/* Enable parity, disable init, still TEST mode */
canREG2->CTL = 0x00002880U;
/* Read location with parity error */
canread = canRAM2;
/* check if ESM group1 channel 23 is flagged */
if ((esmREG->SR1[0U] & 0x00800000U) == 0U)
{
/* No DCAN2 RAM parity error was flagged to ESM */
selftestFailNotification(CAN2PARITYCHECK_FAIL1);
}
else
{
/* clear ESM group1 channel 23 flag */
esmREG->SR1[0U] = 0x00800000U;
/* Disable parity, init mode, TEST mode */
canREG2->CTL = 0x00001481U;
/* Revert back to correct data, flip bit 0 of the parity location */
canPARRAM2 ^= 0x00001000U;
}
/* Disable RAM Direct Access mode */
canREG2->TEST = 0x00000000U;
/* disable TEST mode */
canREG2->CTL = canctl_bk;
/* Read Error and Status register to clear Parity Error bit */
canread = canREG2->ES;
/* USER CODE BEGIN (68) */
/* USER CODE END */
}
/** @fn void checkRAMECC(void)
* @brief Check TCRAM ECC error detection logic.
*
* This function checks TCRAM ECC error detection logic.
*/
/* SourceId : SELFTEST_SourceId_034 */
/* DesignId : SELFTEST_DesignId_019 */
/* Requirements : HL_SR408 */
void checkRAMECC(void)
{
volatile uint64 ramread = 0U;
volatile uint32 regread = 0U;
uint32 tcram1ErrStat, tcram2ErrStat = 0U;
uint64 tcramA1_bk = tcramA1bit;
uint64 tcramB1_bk = tcramB1bit;
uint64 tcramA2_bk = tcramA2bit;
uint64 tcramB2_bk = tcramB2bit;
/* Clear RAMOCUUR before setting RAMTHRESHOLD register */
tcram1REG->RAMOCCUR = 0U;
tcram2REG->RAMOCCUR = 0U;
/* Set Single-bit Error Threshold Count as 1 */
tcram1REG->RAMTHRESHOLD = 1U;
tcram2REG->RAMTHRESHOLD = 1U;
/* Enable single bit error generation */
tcram1REG->RAMINTCTRL = 1U;
tcram2REG->RAMINTCTRL = 1U;
/* Enable writes to ECC RAM, enable ECC error response */
tcram1REG->RAMCTRL = 0x0005010AU;
tcram2REG->RAMCTRL = 0x0005010AU;
/* Force a single bit error in both the banks */
_coreDisableRamEcc_();
tcramA1bitError ^= 1U;
tcramB1bitError ^= 1U;
_coreEnableRamEcc_();
/* Read the corrupted data to generate single bit error */
ramread = tcramA1bit;
ramread = tcramB1bit;
/* Check for error status */
tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U;
tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U;
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U))
{
/* TCRAM module does not reflect 1-bit error reported by CPU */
selftestFailNotification(CHECKRAMECC_FAIL1);
}
else
{
if((esmREG->SR1[0U] & 0x14000000U) != 0x14000000U)
{
/* TCRAM 1-bit error not flagged in ESM */
selftestFailNotification(CHECKRAMECC_FAIL2);
}
else
{
/* Clear single bit error flag in TCRAM module */
tcram1REG->RAMERRSTATUS = 0x1U;
tcram2REG->RAMERRSTATUS = 0x1U;
/* Clear ESM status */
esmREG->SR1[0U] = 0x14000000U;
}
}
/* Force a double bit error in both the banks */
_coreDisableRamEcc_();
tcramA2bitError ^= 3U;
tcramB2bitError ^= 3U;
_coreEnableRamEcc_();
/* Read the corrupted data to generate double bit error */
ramread = tcramA2bit;
ramread = tcramB2bit;
regread = tcram1REG->RAMUERRADDR;
regread = tcram2REG->RAMUERRADDR;
/* disable writes to ECC RAM */
tcram1REG->RAMCTRL = 0x0005000AU;
tcram2REG->RAMCTRL = 0x0005000AU;
/* Compute correct ECC */
tcramA1bit = tcramA1_bk;
tcramB1bit = tcramB1_bk;
tcramA2bit = tcramA2_bk;
tcramB2bit = tcramB2_bk;
}
/* SourceId : SELFTEST_SourceId_042 */
/* DesignId : SELFTEST_DesignId_011 */
/* Requirements : HL_SR401 */
void pbistFail(void)
{
uint32 PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
PBIST_RAMT = pbistREG->RAMT;
PBIST_FSRA0 = pbistREG->FSRA0;
PBIST_FSRDL0 = pbistREG->FSRDL0;
if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
{
memoryPort0TestFailNotification((uint32)((PBIST_RAMT & 0xFF000000U) >> 24U), (uint32)((PBIST_RAMT & 0x00FF0000U) >> 16U),(uint32)PBIST_FSRA0, (uint32)PBIST_FSRDL0);
}
else
{
/* USER CODE BEGIN (77) */
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (78) */
/* USER CODE END */
}
}
/** @fn void errata_PBIST_4(void)
* @brief Workaround for the Errata PBIST#4.
*
* This function is workaround for Errata PBIST#4.
* This function is designed to initialize the ROMs using the PBIST controller.
* The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM.
* This function should be called at startup after system init before using the ROMs.
*
* @note : This Function uses register's which are not exposed to users through
* TRM , to run custom algorithm. User can use this function as Black box.
*
*/
void errata_PBIST_4(void)
{
volatile uint32 i = 0U;
uint8 ROM_count;
sint32 PBIST_wait_done_loop;
uint32 pmuCalibration, pmuCount;
/* PMU calibration */
_pmuEnableCountersGlobal_();
_pmuResetCounters_();
_pmuStartCounters_(pmuCYCLE_COUNTER);
_pmuStopCounters_(pmuCYCLE_COUNTER);
pmuCalibration=_pmuGetCycleCount_();
/* ROM_init Setup using special reserved registers as part of errata fix */
/* (Only to be used in this function) */
#ifdef CEEDLING_TEST
pbistREG->rsvd0[0x0 >> 2] = 0x0000000AU;
pbistREG->rsvd0[0xC >> 2] = 0x0000EE0AU;
#else
*(volatile uint32 *)0xFFFF0400U = 0x0000000AU;
*(volatile uint32 *)0xFFFF040CU = 0x0000EE0AU;
#endif
/* Loop for Executing PBIST ROM and STC ROM */
for (ROM_count = 0U; ROM_count < 2U; ROM_count++)
{
/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;
/* PBIST Clocks did not disable */
if(pbistREG->PACT != 0x0U )
{
selftestFailNotification(PBISTSELFCHECK_FAIL3);
}
else
{
/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000105U;
/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;
/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000010AU;
/* Clear PBIST Done */
systemREG1->MSTCGSTAT = 0x1U;
/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x3U;
/* CPU control of PBIST */
pbistREG->DLR = 0x10U;
/* Load PBIST ALGO to initialize the ROMs */
#ifdef CEEDLING_TEST
pbistREG->rsvd0[0x000U >> 2] = 0x00000001U;
pbistREG->rsvd0[0x040U >> 2] = 0x00000025U;
pbistREG->rsvd0[0x004U >> 2] = 0x62400001U;
pbistREG->rsvd0[0x044U >> 2] = 0x00000004U;
pbistREG->rsvd0[0x008U >> 2] = 0x00068003U;
pbistREG->rsvd0[0x048U >> 2] = 0x00000000U;
pbistREG->rsvd0[0x00CU >> 2] = 0x00000004U;
pbistREG->rsvd0[0x04CU >> 2] = 0x00006860U;
pbistREG->rsvd0[0x010U >> 2] = 0x00000000U;
pbistREG->rsvd0[0x050U >> 2] = 0x00000001U;
pbistREG->rsvd0[0x140U >> 2] = 0x000003E8U;
pbistREG->rsvd0[0x150U >> 2] = 0x00000001U;
pbistREG->rsvd0[0x130U >> 2] = 0x00000000U;
#else
*(volatile uint32 *)0xFFFFE400U = 0x00000001U;
*(volatile uint32 *)0xFFFFE440U = 0x00000025U;
*(volatile uint32 *)0xFFFFE404U = 0x62400001U;
*(volatile uint32 *)0xFFFFE444U = 0x00000004U;
*(volatile uint32 *)0xFFFFE408U = 0x00068003U;
*(volatile uint32 *)0xFFFFE448U = 0x00000000U;
*(volatile uint32 *)0xFFFFE40CU = 0x00000004U;
*(volatile uint32 *)0xFFFFE44CU = 0x00006860U;
*(volatile uint32 *)0xFFFFE410U = 0x00000000U;
*(volatile uint32 *)0xFFFFE450U = 0x00000001U;
*(volatile uint32 *)0xFFFFE540U = 0x000003E8U;
*(volatile uint32 *)0xFFFFE550U = 0x00000001U;
*(volatile uint32 *)0xFFFFE530U = 0x00000000U;
#endif
/* SELECT ROM */
if (ROM_count == 1U)
{
/* SELECT PBIST ROM */
#ifdef CEEDLING_TEST
pbistREG->rsvd0[0x120 >> 2] = 0x00000002U;
pbistREG->rsvd0[0x124 >> 2] = 0x00000000U;
#else
*(volatile uint32 *)0xFFFFE520U = 0x00000002U;
*(volatile uint32 *)0xFFFFE524U = 0x00000000U;
#endif
pbistREG->RAMT = 0x01002008U;
}
else
{
/* SELECT STC ROM */
#ifdef CEEDLING_TEST
pbistREG->rsvd0[0x120 >> 2] = 0xFFF0007CU;
pbistREG->rsvd0[0x124 >> 2] = 0x0A63FFFFU;
#else
*(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU;
*(volatile uint32 *)0xFFFFE524U = 0x0A63FFFFU;
#endif
pbistREG->RAMT = 0x02002008U;
}
/* Setup using special reserved registers as part of errata fix */
/* (Only to be used in this function) */
pbistREG->rsvd1[4U] = 1U;
pbistREG->rsvd1[0U] = 3U;
/* Start PMU counter */
_pmuResetCounters_();
_pmuStartCounters_(pmuCYCLE_COUNTER);
/* PBIST_RUN */
pbistREG->rsvd1[1U] = 1U;
/* wait until memory self-test done is indicated */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* Stop PMU counter */
_pmuStopCounters_(pmuCYCLE_COUNTER);
/* Get CPU cycle count */
pmuCount =_pmuGetCycleCount_();
/* Calculate PBIST test complete time in ROM Clock */
/* 2 - Divide value ( Default is 2 in HALCoGen) */
/* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */
pmuCount = pmuCount - pmuCalibration;
PBIST_wait_done_loop = ((sint32)pmuCount/2) - 1000;
/* Check PBIST status results (Address, Status, Count, etc...) */
if ((pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 |
pbistREG->FSRDL1 | pbistREG->rsvd4[0U] | pbistREG->rsvd4[1U]) != 0U)
{
/* PBIST Failure for the Algorithm chosen above */
selftestFailNotification(PBISTSELFCHECK_FAIL1);
}
/* Check that the algorithm executed in the expected amount of time. */
/* This time is dependent on the ROMCLKDIV selected */
if ((PBIST_wait_done_loop <= 20) || (PBIST_wait_done_loop >= 200) )
{
selftestFailNotification(PBISTSELFCHECK_FAIL2);
}
/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;
/* Disable PBIST */
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
}
} /* ROM Loop */
/* ROM restore default setup */
/* (must be completed before continuing) */
#ifdef CEEDLING_TEST
fmtmREG->rsvd0[0x0C >> 2] = 0x0000AA0AU;
fmtmREG->rsvd0[0x0C >> 2] = 0x0000AA05U;
fmtmREG->rsvd0[0x00 >> 2] = 0x00000005U;
#else
*(volatile uint32 *)0xFFFF040CU = 0x0000AA0AU;
*(volatile uint32 *)0xFFFF040CU = 0x0000AA05U;
*(volatile uint32 *)0xFFFF0400U = 0x00000005U;
#endif
_pmuDisableCountersGlobal_();
}
/** @fn void enableParity(void)
* @brief Enable peripheral RAM parity
*
* This function enables RAM parity for all peripherals for which RAM parity check is enabled.
* This function is called before memoryInit in the startup
*
*/
#pragma WEAK(enableParity)
void enableParity(void)
{
VIM_PARCTL = 0xAU; /* Enable VIM RAM parity */
canREG1->CTL = ((uint32)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */
canREG2->CTL = ((uint32)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */
adcREG1->PARCR = 0xAU; /* Enable ADC1 RAM parity */
adcREG2->PARCR = 0xAU; /* Enable ADC2 RAM parity */
hetREG1->PCR = 0xAU; /* Enable HET1 RAM parity */
}
/** @fn void disableParity(void)
* @brief Disable peripheral RAM parity
*
* This function disables RAM parity for all peripherals for which RAM parity check is enabled.
* This function is called after memoryInit in the startup
*
*/
#pragma WEAK(disableParity)
void disableParity(void)
{
VIM_PARCTL = 0x5U; /* Disable VIM RAM parity */
canREG1->CTL = ((uint32)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */
canREG2->CTL = ((uint32)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */
adcREG1->PARCR = 0x5U; /* Disable ADC1 RAM parity */
adcREG2->PARCR = 0x5U; /* Disable ADC2 RAM parity */
hetREG1->PCR = 0x5U; /* Disable HET1 RAM parity */
}
Hi Luis,
What is confusing me was, the function "fmcECCcheck" is calling only in "fmcBus2Check" function and at the same time "fmcBus2Check" is not calling anywhere else in the code.
So, how we are ending up with the "FMCECCCHECK_FAIL1" issue?
--
Thanks & regards,
Jagadish.
Hi Jagadish,
Thanks for your swift reply an sorry for the incomplete information.
I will try to close the loop:
- "fmcECCcheck()" is called by "fmcBus2Check()" that is defined in "sys_selftest.c"
- "system.c" includes "sys_selftest.h" and also contains the definition of "systemInit()" that calls "fmcBus2Check()"
- "sys_startup.c" includes "system.h" and also contains the definition of "_c_int00()" that calls "systemInit()"
Please find attached the files "sys_startup.c" and "system.c" .
Looking forward to your feedback.
With my best regards,
Luis
/** @file system.c
* @brief System Driver Source File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - API Functions
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "system.h"
#include "sys_selftest.h"
#include "sys_pcr.h"
#include "pinmux.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @fn void systemInit(void)
* @brief Initializes System Driver
*
* This function initializes the System driver.
*
*/
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* SourceId : SYSTEM_SourceId_001 */
/* DesignId : SYSTEM_DesignId_001 */
/* Requirements : HL_SR451 */
void setupPLL(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Disable PLL1 and PLL2 */
systemREG1->CSDISSET = 0x00000002U | 0x00000040U;
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x42U) != 0x42U)
{
#ifdef CEEDLING_TEST
break;
#else
/* Wait */
#endif
}
/* Clear Global Status Register */
systemREG1->GBLSTAT = 0x301U;
/** - Configure PLL control registers */
/** @b Initialize @b Pll1: */
/** - Setup pll control register 1:
* - Setup reset on oscillator slip
* - Setup bypass on pll slip
* - setup Pll output clock divider to max before Lock
* - Setup reset on oscillator fail
* - Setup reference clock divider
* - Setup Pll multiplier
*/
systemREG1->PLLCTL1 = (uint32)0x00000000U
| (uint32)0x20000000U
| (uint32)((uint32)0x1FU << 24U)
| (uint32)0x00000000U
| (uint32)((uint32)(6U - 1U)<< 16U)
| (uint32)(0x7700U);
/** - Setup pll control register 2
* - Setup spreading rate
* - Setup bandwidth adjustment
* - Setup internal Pll output divider
* - Setup spreading amount
*/
systemREG1->PLLCTL2 = (uint32)((uint32)255U << 22U)
| (uint32)((uint32)7U << 12U)
| (uint32)((uint32)(2U - 1U) << 9U)
| (uint32)61U;
/** @b Initialize @b Pll2: */
/** - Setup pll2 control register :
* - setup Pll output clock divider to max before Lock
* - Setup reference clock divider
* - Setup internal Pll output divider
* - Setup Pll multiplier
*/
systemREG2->PLLCTL3 = (uint32)((uint32)(2U - 1U) << 29U)
| (uint32)((uint32)0x1FU << 24U)
| (uint32)((uint32)(6U - 1U)<< 16U)
| (uint32)(0x7700U);
/** - Enable PLL(s) to start up or Lock */
systemREG1->CSDIS = 0x00000000U
| 0x00000000U
| 0x00000008U
| 0x00000080U
| 0x00000000U
| 0x00000000U
| 0x00000000U;
}
/** @fn void trimLPO(void)
* @brief Initialize LPO trim values
*
* Load TRIM values from OTP if present else call customTrimLPO() function
*
*/
/* SourceId : SYSTEM_SourceId_002 */
/* DesignId : SYSTEM_DesignId_002 */
/* Requirements : HL_SR468 */
void trimLPO(void)
{
uint32 u32clocktestConfig;
/* Save user clocktest register configuration */
u32clocktestConfig = systemREG1->CLKTEST;
/* USER CODE BEGIN (4) */
/* USER CODE END */
/*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify what the maximum step is so there is no metric to use for the SW implementation - the routine can temporarily disable the LPOCLKMON range check so the sudden change will not cause a fault.*/
/* Disable clock range detection*/
systemREG1->CLKTEST = (systemREG1->CLKTEST
| (uint32)((uint32)0x1U << 24U))
& (uint32)(~((uint32)0x1U << 25U));
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if(LPO_TRIM_VALUE != 0xFFFFU)
{
systemREG1->LPOMONCTL = (uint32)((uint32)1U << 24U)
| (uint32)((uint32)LPO_TRIM_VALUE);
}
else
{
customTrimLPO();
}
/* Restore the user clocktest register value configuration */
systemREG1->CLKTEST = u32clocktestConfig;
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
/* SourceId : SYSTEM_SourceId_003 */
/* DesignId : SYSTEM_DesignId_003 */
/* Requirements : HL_SR457 */
void setupFlash(void)
{
/* USER CODE BEGIN (6) */
/* USER CODE END */
/** - Setup flash read mode, address wait states and data wait states */
flashWREG->FRDCNTL = 0x00000000U
| (uint32)((uint32)3U << 8U)
| (uint32)((uint32)1U << 4U)
| 1U;
/** - Setup flash access wait states for bank 7 */
FSM_WR_ENA_HL = 0x5U;
EEPROM_CONFIG_HL = 0x00000002U
| (uint32)((uint32)3U << 16U) ;
/* USER CODE BEGIN (7) */
/* USER CODE END */
/** - Disable write access to flash state machine registers */
FSM_WR_ENA_HL = 0xAU;
/** - Setup flash bank power modes */
flashWREG->FBFALLBACK = 0x00000000U
| (uint32)((uint32)SYS_ACTIVE << 14U) /* BANK 7 */
| (uint32)((uint32)SYS_ACTIVE << 2U) /* BANK 1 */
| (uint32)((uint32)SYS_ACTIVE << 0U); /* BANK 0 */
/* USER CODE BEGIN (8) */
/* USER CODE END */
}
/* SourceId : SYSTEM_SourceId_004 */
/* DesignId : SYSTEM_DesignId_004 */
/* Requirements : HL_SR470 */
void periphInit(void)
{
/* USER CODE BEGIN (9) */
/* USER CODE END */
/** - Disable Peripherals before peripheral powerup*/
systemREG1->CLKCNTL &= 0xFFFFFEFFU;
/** - Release peripherals from reset and enable clocks to all peripherals */
/** - Power-up all peripherals */
pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
/** - Enable Peripherals */
systemREG1->CLKCNTL |= 0x00000100U;
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
/* SourceId : SYSTEM_SourceId_005 */
/* DesignId : SYSTEM_DesignId_005 */
/* Requirements : HL_SR469 */
void mapClocks(void)
{
uint32 SYS_CSVSTAT, SYS_CSDIS;
/* USER CODE BEGIN (11) */
/* USER CODE END */
/** @b Initialize @b Clock @b Tree: */
/** - Disable / Enable clock domain */
systemREG1->CDDIS = (uint32)((uint32)0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */
| (uint32)((uint32)0U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */
| (uint32)((uint32)0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */
| (uint32)((uint32)0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */
| (uint32)((uint32)1U << 10U) /* AVCLK3 , 1 - OFF, 0 - ON */
| (uint32)((uint32)0U << 11U); /* AVCLK4 , 1 - OFF, 0 - ON */
/* Work Around for Errata SYS#46:
*
* Errata Description:
* Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
* Workaround:
* Always check the CSDIS register to make sure the clock source is turned on and check
* the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
*/
/** - Wait for until clocks are locked */
SYS_CSVSTAT = systemREG1->CSVSTAT;
SYS_CSDIS = systemREG1->CSDIS;
while ((SYS_CSVSTAT & ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) != ((SYS_CSDIS ^ 0xFFU) & 0xFFU))
{
SYS_CSVSTAT = systemREG1->CSVSTAT;
SYS_CSDIS = systemREG1->CSDIS;
#ifdef CEEDLING_TEST
break;
#endif
} /* Wait */
/* USER CODE BEGIN (12) */
/* USER CODE END */
/** - Map device clock domains to desired sources and configure top-level dividers */
/** - All clock domains are working off the default clock sources until now */
/** - The below assignments can be easily modified using the HALCoGen GUI */
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
systemREG1->GHVSRC = (uint32)((uint32)SYS_OSC << 24U)
| (uint32)((uint32)SYS_OSC << 16U)
| (uint32)((uint32)SYS_PLL1 << 0U);
/** - Setup RTICLK1 and RTICLK2 clocks */
systemREG1->RCLKSRC = (uint32)((uint32)1U << 24U)
| (uint32)((uint32)SYS_VCLK << 16U)
| (uint32)((uint32)1U << 8U)
| (uint32)((uint32)SYS_VCLK << 0U);
/** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
systemREG1->VCLKASRC = (uint32)((uint32)SYS_VCLK << 8U)
| (uint32)((uint32)SYS_VCLK << 0U);
/** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xF0FFFFFFU)
| (uint32)((uint32)1U << 24U);
systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xFFF0FFFFU)
| (uint32)((uint32)1U << 16U);
systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U)
| (uint32)((uint32)1U << 8U)
| (uint32)((uint32)1U << 0U);
systemREG2->VCLKACON1 = (uint32)((uint32)(1U - 1U) << 24U)
| (uint32)((uint32)0U << 20U)
| (uint32)((uint32)SYS_VCLK << 16U)
| (uint32)((uint32)(1U - 1U) << 8U)
| (uint32)((uint32)0U << 4U)
| (uint32)((uint32)SYS_VCLK << 0U);
/* USER CODE BEGIN (13) */
/* USER CODE END */
/* Now the PLLs are locked and the PLL outputs can be sped up */
/* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U);
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U);
/* Enable/Disable Frequency modulation */
systemREG1->PLLCTL2 |= 0x00000000U;
/* USER CODE BEGIN (14) */
/* USER CODE END */
}
/* SourceId : SYSTEM_SourceId_006 */
/* DesignId : SYSTEM_DesignId_006 */
/* Requirements : HL_SR471 */
void systemInit(void)
{
uint32 efcCheckStatus;
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
setupPLL();
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheckStatus = efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Enable clocks to peripherals and release peripheral reset */
periphInit();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
if(efcCheckStatus == 0U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
}
else if(efcCheckStatus == 2U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
else
{
selftestFailNotification(EFCCHECK_FAIL2);
}
}
else
{
/* Empty */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
setupFlash();
/* USER CODE BEGIN (21) */
/* USER CODE END */
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/* USER CODE BEGIN (22) */
/* USER CODE END */
/** - Check if there was an ESM error from FMC OTP read during power-up */
fmcBus2Check();
/* USER CODE BEGIN (23) */
/* USER CODE END */
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();
/* USER CODE BEGIN (24) */
/* USER CODE END */
/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)(8U - 1U) & 0xFFFFU);
/* USER CODE BEGIN (25) */
/* USER CODE END */
}
/* SourceId : SYSTEM_SourceId_007 */
/* DesignId : SYSTEM_DesignId_007 */
/* Requirements : HL_SR493 */
void systemPowerDown(uint32 mode)
{
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Disable clock sources */
systemREG1->CSDISSET = mode & 0x000000FFU;
/* Disable clock domains */
systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;
/* Idle CPU */
_gotoCPUIdle_();
/* USER CODE BEGIN (27) */
/* USER CODE END */
}
/* USER CODE BEGIN (28) */
/* USER CODE END */
/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration registers
*
* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
* @param[in] type: whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
*
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : SYSTEM_SourceId_008 */
/* DesignId : SYSTEM_DesignId_008 */
/* Requirements : HL_SR506 */
void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE;
config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE;
config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE;
config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE;
config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE;
config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE;
config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE;
config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE;
config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE;
config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE;
config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE;
config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE;
config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE;
config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2;
config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE;
config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE;
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if(LPO_TRIM_VALUE != 0xFFFFU)
{
config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1;
}
else
{
config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2;
}
config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE;
config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE;
config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE;
config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE;
config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE;
config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE;
config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE;
config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE;
config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE;
config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE;
config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE;
config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2;
config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE;
config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE;
config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE;
config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE;
config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE;
}
else
{
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1;
config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2;
config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7;
config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8;
config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9;
config_reg->CONFIG_CSDIS = systemREG1->CSDIS;
config_reg->CONFIG_CDDIS = systemREG1->CDDIS;
config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC;
config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC;
config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC;
config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR;
config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR;
config_reg->CONFIG_MSINENA = systemREG1->MSINENA;
config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1;
config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2;
config_reg->CONFIG_UERFLAG = systemREG1->SYSPC10;
config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL;
config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST;
config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1;
config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2;
config_reg->CONFIG_GPREG1 = systemREG1->GPREG1;
config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR;
config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1;
config_reg->CONFIG_MMUGCR = systemREG1->CPURSTCR;
config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL;
config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL;
config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1;
config_reg->CONFIG_SYSECR = systemREG1->SYSECR;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3;
config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV;
config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL;
config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1;
config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP;
config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN;
}
}
/** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration registers
*
* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
* @param[in] type: whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
*
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : SYSTEM_SourceId_009 */
/* DesignId : SYSTEM_DesignId_009 */
/* Requirements : HL_SR506 */
void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE;
config_reg->CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE;
config_reg->CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE;
config_reg->CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE;
config_reg->CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE;
config_reg->CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE;
config_reg->CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE;
config_reg->CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE;
config_reg->CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE;
config_reg->CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE;
config_reg->CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE;
config_reg->CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE;
config_reg->CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE;
config_reg->CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE;
}
else
{
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
config_reg->CONFIG_FRDCNTL = flashWREG->FRDCNTL;
config_reg->CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1;
config_reg->CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2;
config_reg->CONFIG_FEDACSDIS = flashWREG->FEDACSDIS;
config_reg->CONFIG_FBPROT = flashWREG->FBPROT;
config_reg->CONFIG_FBSE = flashWREG->FBSE;
config_reg->CONFIG_FBAC = flashWREG->FBAC;
config_reg->CONFIG_FBFALLBACK = flashWREG->FBFALLBACK;
config_reg->CONFIG_FPAC1 = flashWREG->FPAC1;
config_reg->CONFIG_FPAC2 = flashWREG->FPAC2;
config_reg->CONFIG_FMAC = flashWREG->FMAC;
config_reg->CONFIG_FLOCK = flashWREG->FLOCK;
config_reg->CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL;
config_reg->CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2;
}
}
/** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration registers
*
* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
* @param[in] type: whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
*
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : SYSTEM_SourceId_010 */
/* DesignId : SYSTEM_DesignId_010 */
/* Requirements : HL_SR506 */
void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_RAMCTRL[0U] = SRAM_RAMCTRL_CONFIGVALUE;
config_reg->CONFIG_RAMTHRESHOLD[0U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
config_reg->CONFIG_RAMINTCTRL[0U] = SRAM_RAMINTCTRL_CONFIGVALUE;
config_reg->CONFIG_RAMTEST[0U] = SRAM_RAMTEST_CONFIGVALUE;
config_reg->CONFIG_RAMADDRDECVECT[0U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
config_reg->CONFIG_RAMCTRL[1U] = SRAM_RAMCTRL_CONFIGVALUE;
config_reg->CONFIG_RAMTHRESHOLD[1U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
config_reg->CONFIG_RAMINTCTRL[1U] = SRAM_RAMINTCTRL_CONFIGVALUE;
config_reg->CONFIG_RAMTEST[1U] = SRAM_RAMTEST_CONFIGVALUE;
config_reg->CONFIG_RAMADDRDECVECT[1U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
}
else
{
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
config_reg->CONFIG_RAMCTRL[0U] = tcram1REG->RAMCTRL;
config_reg->CONFIG_RAMTHRESHOLD[0U] = tcram1REG->RAMTHRESHOLD;
config_reg->CONFIG_RAMINTCTRL[0U] = tcram1REG->RAMINTCTRL;
config_reg->CONFIG_RAMTEST[0U] = tcram1REG->RAMTEST;
config_reg->CONFIG_RAMADDRDECVECT[0U] = tcram1REG->RAMADDRDECVECT;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
config_reg->CONFIG_RAMCTRL[1U] = tcram2REG->RAMCTRL;
config_reg->CONFIG_RAMTHRESHOLD[1U] = tcram2REG->RAMTHRESHOLD;
config_reg->CONFIG_RAMINTCTRL[1U] = tcram2REG->RAMINTCTRL;
config_reg->CONFIG_RAMTEST[1U] = tcram2REG->RAMTEST;
config_reg->CONFIG_RAMADDRDECVECT[1U] = tcram2REG->RAMADDRDECVECT;
}
}
/** @fn customTrimLPO(void)
* @brief custom function to initilize LPO trim values
*
* This function initializes default LPO trim values if OTP value is 0XFFFF,
* user can also write their own code to handle this case .
*
*/
void customTrimLPO(void)
{
/* User can write logic to handle the case where LPO trim is set to 0xFFFFu */
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* Load default trimLPO value */
systemREG1->LPOMONCTL = (uint32)((uint32)1U << 24U)
| (uint32)((uint32)16U << 8U)
| (uint32)((uint32)16U);
/* USER CODE BEGIN (30) */
/* USER CODE END */
}
/** @file sys_startup.c
* @brief Startup Source File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Include Files
* - Type Definitions
* - External Functions
* - VIM RAM Setup
* - Startup Routine
* .
* which are relevant for the Startup.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
#include "system.h"
#include "sys_vim.h"
#include "sys_core.h"
#include "sys_selftest.h"
#include "esm.h"
#include "mibspi.h"
#include "errata_SSWF021_45.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* External Functions */
/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
#ifdef CEEDLING_TEST
extern int main_test(void);
#else
extern int main(void);
#endif
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(int _status);
void afterSTC(void);
/* USER CODE BEGIN (3) */
/* USER CODE END */
void handlePLLLockFail(void);
/* Startup Routine */
void _c_int00(void);
#define PLL_RETRIES 5U
/* USER CODE BEGIN (4) */
/* USER CODE END */
#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)
/* SourceId : STARTUP_SourceId_001 */
/* DesignId : STARTUP_DesignId_001 */
/* Requirements : HL_SR508 */
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (9) */
/* USER CODE END */
/* Enable response to ECC errors indicated by CPU for accesses to flash */
flashWREG->FEDACCTRL1 = 0x000A060AU;
/* USER CODE BEGIN (10) */
/* USER CODE END */
/* Enable CPU ECC checking for ATCM (flash accesses) */
_coreEnableFlashEcc_();
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Workaround for Errata CORTEXR4 66 */
_errata_CORTEXR4_66_();
/* Workaround for Errata CORTEXR4 57 */
_errata_CORTEXR4_57_();
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
/* check for power-on reset condition */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Add condition to check whether PLL can be started successfully */
if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
{
/* Put system in a safe state */
handlePLLLockFail();
}
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* USER CODE BEGIN (13) */
/* USER CODE END */
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* reset could be caused by stcSelfCheck run or by an actual CPU self-test run */
/* check if this was an stcSelfCheck run */
if ((stcREG->STCSCSCR & 0xFU) == 0xAU)
{
/* check if the self-test fail bit is set */
if ((stcREG->STCGSTAT & 0x3U) != 0x3U)
{
/* STC self-check has failed */
stcSelfCheckFail();
}
/* STC self-check has passed */
else
{
/* clear self-check mode */
stcREG->STCSCSCR = 0x05U;
/* clear STC global status flags */
stcREG->STCGSTAT = 0x3U;
/* clear ESM group1 channel 27 status flag */
esmREG->SR1[0U] = 0x08000000U;
/* Start CPU Self-Test */
cpuSelfTest(STC_INTERVAL, STC_MAX_TIMEOUT, TRUE);
}
}
/* CPU reset caused by CPU self-test completion */
else if ((stcREG->STCGSTAT & 0x1U) == 0x1U)
{
/* Self-Test Fail flag is set */
if ((stcREG->STCGSTAT & 0x2U) == 0x2U)
{
/* Call CPU self-test failure handler */
cpuSelfTestFail();
}
/* CPU self-test completed successfully */
else
{
/* clear STC global status flag */
stcREG->STCGSTAT = 0x1U;
/* Continue start-up sequence after CPU STC completed */
afterSTC();
}
}
/* CPU reset caused by software writing to CPU RESET bit */
else
{
/* Add custom routine here to handle the case where software causes CPU reset */
}
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->SR1[2]) != 0U)
{
/* USER CODE BEGIN (24) */
#if 0
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (25) */
#endif
/* USER CODE END */
}
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* Workaround for Errata PBIST#4 */
errata_PBIST_4();
/* Run a diagnostic check on the memory self-test controller.
* This function chooses a RAM test algorithm and runs it on an on-chip ROM.
* The memory self-test is expected to fail. The function ensures that the PBIST controller
* is capable of detecting and indicating a memory self-test failure.
*/
pbistSelfCheck();
/* Run PBIST on STC ROM */
pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for STC ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* Check if PBIST on STC ROM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* PBIST and STC ROM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
pbistFail();
}
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* Run PBIST on PBIST ROM */
pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for PBIST ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* Check if PBIST ROM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* PBIST and STC ROM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
pbistFail();
}
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/* Make sure that the CPU self-test controller can actually detect a fault inside CPU */
stcSelfCheck();
/* USER CODE BEGIN (28) */
/* USER CODE END */
}
void afterSTC(void)
{
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* Make sure that CCM-R4F is working as expected.
* This function puts the CCM-R4F module through its self-test modes.
* It ensures that the CCM-R4F is indeed capable of detecting a CPU mismatch,
* and is also capable of indicating a mismatch error to the ESM.
*/
ccmSelfCheck();
/* USER CODE BEGIN (30) */
/* USER CODE END */
/* USER CODE BEGIN (31) */
/* USER CODE END */
/* Disable RAM ECC before doing PBIST for Main RAM */
_coreDisableRamEcc_();
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x00300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (33) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
/* USER CODE BEGIN (34) */
/* USER CODE END */
pbistFail();
/* USER CODE BEGIN (35) */
/* USER CODE END */
}
/* USER CODE BEGIN (36) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (37) */
/* USER CODE END */
/* Initialize CPU RAM.
* This function uses the system module's hardware for auto-initialization of memories and their
* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
* Hence the value 0x1 passed to the function.
* This function will initialize the entire CPU RAM and the corresponding ECC locations.
*/
memoryInit(0x1U);
/* USER CODE BEGIN (38) */
/* USER CODE END */
/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
_coreEnableRamEcc_();
/* USER CODE BEGIN (39) */
/* USER CODE END */
/* Start PBIST on all dual-port memories */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
pbistRun( (uint32)0x00000000U /* EMAC RAM */
| (uint32)0x00000000U /* USB RAM */
| (uint32)0x00000000U /* DMA RAM */
| (uint32)0x00000200U /* VIM RAM */
| (uint32)0x00000000U /* MIBSPI1 RAM */
| (uint32)0x00000000U /* MIBSPI3 RAM */
| (uint32)0x00000000U /* MIBSPI5 RAM */
| (uint32)0x00000004U /* CAN1 RAM */
| (uint32)0x00000008U /* CAN2 RAM */
| (uint32)0x00000000U /* CAN3 RAM */
| (uint32)0x00000400U /* ADC1 RAM */
| (uint32)0x00020000U /* ADC2 RAM */
| (uint32)0x00001000U /* HET1 RAM */
| (uint32)0x00000000U /* HET2 RAM */
| (uint32)0x00000000U /* HTU1 RAM */
| (uint32)0x00000000U /* HTU2 RAM */
| (uint32)0x00000000U /* RTP RAM */
| (uint32)0x00000000U /* FRAY RAM */
,(uint32) PBIST_March13N_DP);
/* USER CODE BEGIN (40) */
/* USER CODE END */
/* Test the CPU ECC mechanism for RAM accesses.
* The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
* in the ECC causes a data abort exception. The data abort handler is written to look for
* deliberately caused exception and to return the code execution to the instruction
* following the one that caused the abort.
*/
checkRAMECC();
/* USER CODE BEGIN (41) */
/* USER CODE END */
/* Test the CPU ECC mechanism for Flash accesses.
* The checkFlashECC function uses the flash interface module's diagnostic mode 7
* to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
* error on reading from flash causes a data abort exception.
* The data abort handler is written to look for deliberately caused exception and
* to return the code execution to the instruction following the one that was aborted.
*
*/
checkFlashECC();
flashWREG->FDIAGCTRL = 0x000A0007U; /* disable flash diagnostic mode */
/* USER CODE BEGIN (42) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
#ifdef CEEDLING_TEST
break;
#endif
}/* Wait */
/* USER CODE BEGIN (44) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* USER CODE BEGIN (45) */
/* USER CODE END */
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
/* USER CODE BEGIN (46) */
/* USER CODE END */
pbistFail();
/* USER CODE BEGIN (47) */
/* USER CODE END */
}
/* USER CODE BEGIN (48) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (55) */
/* USER CODE END */
/* USER CODE BEGIN (56) */
/* USER CODE END */
/* Enable parity on selected RAMs */
enableParity();
/* Initialize all on-chip SRAMs except for MibSPIx RAMs
* The MibSPIx modules have their own auto-initialization mechanism which is triggered
* as soon as the modules are brought out of local reset.
*/
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
*/
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
memoryInit( (uint32)((uint32)0U << 1U) /* DMA RAM */
| (uint32)((uint32)1U << 2U) /* VIM RAM */
| (uint32)((uint32)1U << 5U) /* CAN1 RAM */
| (uint32)((uint32)1U << 6U) /* CAN2 RAM */
| (uint32)((uint32)0U << 10U) /* CAN3 RAM */
| (uint32)((uint32)1U << 8U) /* ADC1 RAM */
| (uint32)((uint32)1U << 14U) /* ADC2 RAM */
| (uint32)((uint32)1U << 3U) /* HET1 RAM */
| (uint32)((uint32)0U << 4U) /* HTU1 RAM */
| (uint32)((uint32)0U << 15U) /* HET2 RAM */
| (uint32)((uint32)0U << 16U) /* HTU2 RAM */
);
/* Disable parity */
disableParity();
/* Test the parity protection mechanism for peripheral RAMs
NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
/* USER CODE BEGIN (57) */
/* USER CODE END */
het1ParityCheck();
/* USER CODE BEGIN (61) */
/* USER CODE END */
adc1ParityCheck();
/* USER CODE BEGIN (62) */
/* USER CODE END */
adc2ParityCheck();
/* USER CODE BEGIN (63) */
/* USER CODE END */
can1ParityCheck();
/* USER CODE BEGIN (64) */
/* USER CODE END */
can2ParityCheck();
/* USER CODE BEGIN (66) */
/* USER CODE END */
vimParityCheck();
/* USER CODE BEGIN (68) */
/* USER CODE END */
/* USER CODE BEGIN (72) */
/* Interrupts are handled in the traditional way for this project, i.e. by
* making the CPU branch to 0x18 instead of directly to the ISR via the VIC.
*/
#if 0
/* USER CODE END */
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* USER CODE BEGIN (73) */
#endif
/* USER CODE END */
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (74) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
/* initialize copy table */
__TI_auto_init();
/* USER CODE BEGIN (75) */
/* USER CODE END */
/* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
#ifdef CEEDLING_TEST
main_test();
#else
main();
#endif
/* USER CODE BEGIN (76) */
/* main() never returns so calling exit afterwards is pointless and just wastes memory. */
#if 0
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
exit(0);
/* USER CODE BEGIN (77) */
#endif
/* USER CODE END */
}
/* USER CODE BEGIN (78) */
/* USER CODE END */
/** @fn void handlePLLLockFail(void)
* @brief This function handles PLL lock fail.
*/
void handlePLLLockFail(void)
{
/* USER CODE BEGIN (79) */
#ifdef CEEDLING_TEST
return;
#else
/* USER CODE END */
while(1)
{
}
/* USER CODE BEGIN (80) */
#endif
/* USER CODE END */
}
/* USER CODE BEGIN (81) */
/* USER CODE END */
Hi Luis,
Thanks for the code and details, to be honest i never called this "fmcBus2Check" function before and tested.
I will try to test it now and will provide you an update.
--
Thanks & regards,
Jagadish.
Hi Luis,
Apologies for the delay, i am on vacation till today.
I will work on this issue now and will provide you an update ASAP.
--
Thanks & regards,
Jagadish.
Hi Luis,
I don't have TMS570LS1227 board, so i tried to test your issue on RM46 and i created a project as per your data.
And here i am not seeing the issue you are mentioned. The code never ends up at FMCECCCHECK_FAIL1.
Can you please check my verify my code and guide me if i miss something.
--
Thanks & regards,
Jagadish.
Hi Jagadish,
Firstly, sorry for the delayed response!
I opened the project and tried to figure out where in the project my original question is verified, and I can't figure out where (file and line) the RESET1(bit 15) in System Exception Control Register (SYSECR) is set.
Could you please point me to the file/line where the bit RESET1 is set, or if it is not the case, the rationale behind the code in sys_main.c you provided—w.r.t. the original question about SYSECR bit set?
Thanks for your time and support.
Best regards,
Luis
Hi Luis,
I opened the project and tried to figure out where in the project my original question is verified, and I can't figure out where (file and line) the RESET1(bit 15) in System Exception Control Register (SYSECR) is set.
Could you please point me to the file/line where the bit RESET1 is set, or if it is not the case, the rationale behind the code in sys_main.c you provided—w.r.t. the original question about SYSECR bit set?
I didn't add the RESET code, i just tried by resetting from debugger it self. Can you please confirm that, can i add the reset code on main loop?
I added in main function before calling while(1) and still i couldn't reproduce the issue you are talking about. And behavior was same.
--
Thanks & regards,
Jagadish.
Hello Jagadish,
Thanks for your support.
To answer precisely, I will perform some additional testing on our application and come back to you once I have more findings.
With my best regards,
Luis