Hello,
I have a customer who wanted some clarification on the PMCU_ERR_06. The workaround stated in the errata document is for the CPU and DMA to not access flash simultaneously. How is this possible? If you're executing code from flash while the DMA is transferring data from flash to SRAM wouldn't this violate the workaround condition?
Does this mean that DMA can't be used to copy from flash to other memory locations?
The description also has a comment around not accessing the flash with DMA while an erase operation is in effect. So is this condition limited to when the CPU is actively interacting with the flash controller, or is this errata in effect for all types of flash access (read, write, erase)?
Munan
