TMS570LC4357: Compatibility mode SPI DMA hold CS active

Hi Spencer,

For this requirement you can do one thing, instead of doing 8bit transfers from DMA you can do the 32 bit transfers from DMA  to the "SPIDAT1" register.

Using this way you can get full control over the CSHOLD bit, that means you can decide what should be the CSHOLD bit value for each transfer from DMA.

For example:

In my recent thread one customer asked for 24bit transfer from SPI using DMA, actually 24 bit transfer will not possible directly from SPI as it supports max of 16bit transfer only.

So what we did was we created a 32 bit transfers from DMA to SPIDATA1 register and in that transfer we made CSHOLD = 1 for first two times and on third time we made CSHOLD = 0 that means CS activate for every 3 byte transfer.

If you verify above tx_data array there you can see the 28th bit (CS_HOLD) value in each data.

As a result we got this kind of output:

You can see CS line activated only after 24bit transfer and CS was in hold state for every 3 bytes.

I am providing my code here, you can verify and modify for your requirement:

3005.SPI_DMA_TEST_LC4357 (2).zip

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Thanks & regards,
Jagadish.

Thanks for the response. I am looking for something a little different than the solution you provided. The first 3 bytes are simply appended to the beginning of the buffer I need to send. Below is a capture of using SPI without DMA where I held CS low (The pulses on CS are just noise, not actually toggling). In this scenario I hold CS low for as long as I need.

I've made some progress in this. First I had a typo in copying over code from halcogen to start my SPI transfer and wasn't setting CS HOLD properly. After this I just had to make some logic to reset the CS HOLD which leads to the next point.

In order to set CS hold inactive again, I set up an interrupt on the TX channel for LFS (Last Frame Start) and can set the CS HOLD bit in the SPI DAT1 registers. However, this is one frame too late (I am sending 1 element or 1 byte per frame, and frame count is the length of all the data I am sending). Because setting CS HOLD will only affect the following frame by setting the CS pin inactive after the next SPI tx. So currently, the DMA allows SPI to send 1 extra byte before setting the CS pin inactive which causes problems.

So any extra knowledge to force the CS pin inactive using either the BTC or LFS interrupts would be helpful. I would prefer to avoid using the GIO functionality of the CS pin since SPI reads are still being done by the CPU and that utilizes the SPI functionality of all the pins.

EDIT:
This actually only seems to occur on the first SPI DMA transfer, the rest are okay somehow. The first picture below is what I want to achieve at the end of the SPI Transmit. The second picture is what I am getting (duplicated final byte as the CS is held low one extra transmission). Currently setting CS HOLD to inactive with the LFS interrupt.