Part Number: LP-AM243
How to program the Cortex-R5 debug unit in am243? For example, how to configure debug related registers to enable single step operation? Please provide specific code
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Hi guxl24,
Can you please explain the same in-detail ?
Cortex-R5 debug unit
What do you mean by this ? Are you talking about "DAP" ?
Best Regards,
Aakash
Hi guxl24
As per the Cortex-R5 TRM (Cortex-R5 and Cortex-R5F Technical Reference Manual r1p1 (arm.com)), Debug chapter (chapter 12) says that debug registers can be accessed using memory mapped mode and some of them can be accessed using CP14 registers. Using memory mapped mode is not straight forward as this would require traversing though the ROM table. However, if only the following registers are required to access then Cp14 interface can be used:

But when I use MCR or MRC to access the registers of DBGDSCRxet, DBGDRCR, DBGBVR, DBGBCR as the picture shows, it will resut in an undefined exception. And I have checked that the code was executed in system mode, which is PL1 with a privilege level of PL1.


it will resut in an undefined exception.
so, when executing those MCR, R5 is interrupted by an undefined exception?
Can you share the document from which you took the 1st image. The reason why I asked this is because, R5 TRM only supports CP14 interface only for the following register:

However, the code above is trying to access registers which are not listed in the above registers (and are labeled as memory-mapped debug registers).
To access the memory-mapped debug registers, generally it is required to traverse ROM table and then get the memory location then access the memory-mapped debug registers.
Thanks
Can you share your TRM/Document? Because in R5 TRM, it specifically says that the highlighted registers are memory mapped registers.
Thanks
Hi thanks,
The table shows how to access those registers using CP14 interface. However, that table takes in the assumption that those register are accessible via CP14 interface.
In the same RTM, table C6-5 titled "Debug registers required visibility " shows if that register is visible via CP14 interface or not.

and as per the table, it is not and this is what is being seen in the code itself i.e. when trying to access these particular registers via CP14 interface, an undefined exception is pushed because accessing these register are not supported by Crotex-r5 (Maybe it is supported in Cortex-A! )
These partiular registers can only be accessed by memory map interface.
Hi
The SDK doesn't provide the interface.
No, there is no SDK example as of now.
Why do you say that these register are not supported by Crotex-r5?
In Cortex-R5, the info of which registers can be accessed via CP14 register or not is give.
Registers that can be accessed via CP14 register are: https://developer.arm.com/documentation/ddi0460/d/Debug/Debug-register-interface/Coprocessor-registers-summary?lang=en
registers that are accessed via memory mapped interface are: https://developer.arm.com/documentation/ddi0460/d/Debug/Debug-register-interface/Memory-mapped-registers?lang=en
Another question, this table does not mention that these registers of DBGDSCRxet, DBGDRCR, DBGBVR, DBGBCR cannot be accessed using CP14.
The image that I have attached does not contains complete list. One needs to check the documentation for complete list.