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TM4C129ENCPDT: EPI operation SDRAM affects the input capture CCP, causing frequency jumps

Part Number: TM4C129ENCPDT

Hi Team,

Here's an issue from the customer may need your help:

I use the input capture function of the CCP pin to capture the rising edge of the 50Hz signal, and calculate the signal period based on the time difference between the two captures.

If EPI is not used to expand the SDRAM, the calculation accuracy can meet the 0.002Hz accuracy requirement. After the SDRAM is expanded, the frequency will jump because the instantaneous value of the analog quantity will be stored in the SDRAM, with a frequency of 50*16 or 50*64Hz.

It is speculated that the bus is occupied when reading and writing SDRAM or SDRAM refresh, or the interrupt is temporarily turned off, causing the input capture time of the CCP pin to be inaccurate, causing the final calculated signal period to be inaccurate and causing transitions.

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Thanks & Regards

  • If EPI is not used to expand the SDRAM, the calculation accuracy can meet the 0.002Hz accuracy requirement. After the SDRAM is expanded, the frequency will jump because the instantaneous value of the analog quantity will be stored in the SDRAM, with a frequency of 50*16 or 50*64Hz.
    It is speculated that the bus is occupied when reading and writing SDRAM or SDRAM refresh, or the interrupt is temporarily turned off, causing the input capture time of the CCP pin to be inaccurate, causing the final calculated signal period to be inaccurate and causing transitions.

    Hi Yale,

      50Hz means 20mS. This means an edge will be captured and an interrupt will be generated every 20mS. You also said that the period that is to be written to SDRAM is either 50*16 or 50*64. There is a 4x difference between these two values.  Now look at the SDRAM refresh cycle which is 64mS. If you divide 64 by 20, it is roughly 3.2. This seemingly correlates with the two different periods (50*16 vs 50*64). In another word, it is very possible that the write to SDRAM is being waited due to the refresh cycle while there are 3 more edges being captured. You should be able to use the logic analyzer to see how many edges happened while the refresh cycle is active. 

      I will suggest you buffer the data first before sending to SDRAM. 

    11.4.2.2 Refresh Configuration
    The refresh count is based on the external clock speed and the number of rows per bank as well
    as the refresh period. The RFSH field represents how many external clock cycles remain before an
    AUTO-REFRESH is required. The normal formula is:
    RFSH = (tRefresh_us / number_rows) / ext_clock_period
    A refresh period is normally 64 ms, or 64000 μs. The number of rows is normally 4096 or 8192. The
    ext_clock_period is a value expressed in μsec and is derived by dividing 1000 by the clock speed

  • Hi Charles,

    Thanks for your reply. The reply from the customer:

    Maybe the problem I described above did not highlight the key points. 

    Input capture is a hardware module. When the configured edge arrives, the hardware automatically saves the current timer value, and then calculates the interval between two times based on the timer value captured last time and the timer value captured this time in interrupt or polling. Then calculate the signal frequency.

    The problem now is that the external expansion of SDRAM affects the input capture, that is, the timer value automatically captured by the hardware when an edge jump occurs is not the instantaneous value when the jump occurs.

    The above reply mentioned the update clock of SDRAM, such as 64ms. This is determined by the hardware and cannot be changed. The 50*16 or 50*64Hz I mentioned in the previous question just refers to the frequency at which I save or read the data in SDRAM. This may also be any other frequency, such as randomly defining some variables in SDRAM. The program operation variable may be random, but if it is used in this way, the automatic input capture will be inaccurate, resulting in a larger error in the calculated signal frequency.

    --

    Thanks & Regards

  • The problem now is that the external expansion of SDRAM affects the input capture, that is, the timer value automatically captured by the hardware when an edge jump occurs is not the instantaneous value when the jump occurs.

    Hi Yale,

      Are you using SDRAM for storing data or you are running code out of SDRAM?

      I can't really relate the timer input capture to an ongoing EPI operation. The timer module and the EPI are independent to each other.  The only thing I can think of which I explained in the last reply is that when a timer input capture detects an edge, it will generate an interrupt. The processor is supposed to service the interrupt. If for whatever reason, the timer interrupt is disabled or you are in the middle of a read operation while the refresh is going on. This may hold that CPU read in a wait state. I will suggest you look at the waveform to see this is the case, meaning how many input edges have happened while a SDRAM refresh cycle is going on.