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Compatibility Mode SPI and DMA with Element Count more than 1 using 16-Bit SPI Transfer

Pashan None
Genius 5660 points

Hello Support,

Is there any way I can use Compatibility Mode SPI with DMA using 16-Bit SPI Transfer where the DMA Control Packet has ELEMENT Count as 2 instead of usual 1?

I want to use TTYPE = FRAME_TRANSFER.

DMA READ/WRITE Elelement Size if 16_BIT.

How to synchronize between DMA Transfer to SPI TXDATA field of DAT0 register [3-Pin Mode of SPI] when ELEMENT Count is 2 instead of 1?

Any detailed information will help me.

I can use it with ELEMENT Count of 1 without any issue.

But I need to use ELEMENT Count of 2 due to Slave Device requirements of toggling ChipSelect at 32-Bit boundary of SPI Message.

If I can use ELEMENT Count as 2, then I can use FTCA Interrupt to toggle the Chip Select Pin in 3-Pin Mode of SPI.

Thank  you.

Regards

Pashan

 

  • 0
    TI__Genius 13810 points

    How about using the multi-buffer mode? I think it is easier to do in this way.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Genius 5660 points

    Hello Haixiao,

    In my 128-Pin device there is only one MibSPI1 and SPI2/SPI3 doesn't have Multi-Buffer.

    MibSPI1 is being used for other devices.

    I must use SPI2 for this special IO.

    SPI2 and SPI3 have only 3-Pin Mode due to device package pin. No auto Chip-Select.

    I am using GPIO based Chip Select.

    Any help is appreciated in order to use DMA for this 32-Bit Chip Select controlled SPI Message transfer.

    Thank you.

    Pashan

     

  • 0 in reply to Pashan None
    TI__Genius 13810 points

    It might be possible to use the software DMA trigger mode.

    1. Make sure both the TX shift register and the TX buffer is empty. Check the TX buffer is easy. But I don't have a good method to check the shift-register. Once you receive the spi data, the shift register shoud be clean if no more data is written because the master send out SPI data half a clock cycle ahead of receive the data.

    2. Trigger the DMA. Since we have a shift register and a TX buffer, it should be fine.

    Regards,

    Haixiao