MSPM0G1507: Does TIMA include a feature to drive PWM outputs low when the CPU is in a debug halt state?

rperezti

Part Number: MSPM0G1507

Our system uses TIMA PWM outputs to drive the gates on high current FETs and it would be helpful to force these PWMs low whenever the CPU hits a breakpoint on the debugger. Does such a feature exist for TIMA PWMs? I only see the usual FREE/SOFT bits in the PDBGCTL register which affect the overall peripheral behavior during a halt.

over 1 year ago

+1 Jace H over 1 year ago

TI__Guru 56685 points

Hey Ruben,

I do not see a way of directly controlling the outputs when debugging. There is the PDBGCTL register and the bit in the Counter control register that dictates what happens when you resume from debug, but nothing on direct timer output unfortunately.

0 rperezti over 1 year ago in reply to Jace H

TI__Genius 12375 points

Thanks Jace.

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MSPM0G1507: Does TIMA include a feature to drive PWM outputs low when the CPU is in a debug halt state?