AM263P4: Problems with L2 CPSW example in SDK

Steven Hansen

Part Number: AM263P4

Hi, we are evaluating the CPSW peripheral on AM263Px for a gigabit application and are struggling getting the Layer 2 CPSW example to work. Here is my setup:

MCU+ SDK v9.01.00.20

AM263Px Control Card rev E2 with 180 pin HSEC docking station

Booting in OSPI mode with SBL NULL flashed

Using "Enet Layer 2 CPSW" example from MCU+ SDK (no changes, compiled in release mode)

Loading binary to ControlCard via CCS+JTAG

Direct Ethernet connection between ControlCard and development computer

Using ColaSoft Packet Builder to send packets (ARP packet type with Destination Address set to match ControlCard MAC and Source Address set to match development computer MAC)

Problem:

When running the "Enet Layer 2 CPSW" example, after sending ARP packets from development machine to ControlCard (using ColaSoft Packet Builder per MCU+ docs), the CPSW statistics always show zero. Wireshark shows the ARP packets from PacketBuilder are transmitted but the development computer does not receive any reply from the AM263Px ControlCard.

Here is the output from the AM263Px CC:

INFO: Bootloader_socLoadHsmRtFw:82: Device Type : HSFS  

 [HSM_CLIENT] New Client Registered with Client Id = 0
 INFO: Bootloader_socLoadHsmRtFw:84: HSMRT Size in Bytes : 23875 
INFO: Bootloader_socLoadHsmRtFw:97: hsm runtime firmware load complete ... 
Starting NULL Bootloader ... 
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f0-1 is initialized to 400000000 Hz !!!
[BOOTLOADER_PROFILE] Boot Media       : undefined 
[BOOTLOADER_PROFILE] Boot Image Size  : 0 KB 
[BOOTLOADER_PROFILE] Cores present    : 
[BOOTLOADER PROFILE] System_init                      :         70us 
[BOOTLOADER PROFILE] Drivers_open                     :         40us 
[BOOTLOADER PROFILE] LoadHsmRtFw                      :      31939us 
[BOOTLOADER_PROFILE] SBL Total Time Taken             :      56138us 

NULL Bootloader Execution Complete... 
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...

==========================
     Layer 2 CPSW Test    
==========================

Init all peripheral clocks
----------------------------------------------

Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task

Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 

Init all configs
----------------------------------------------
cpsw-3g: init config
cpsw-3g: Open port 2
EnetPhy_bindDriver: PHY 0: OUI:080028 Model:0f Ver:03 <-> 'dp83869' : OK
PHY 0 is alive

Attach core id 0 on all peripherals
----------------------------------------------
cpsw-3g: Attach core
cpsw-3g: Open DMA
initQs() txFreePktInfoQ initialized with 16 pkts
cpsw-3g: Waiting for link up...
Cpsw_handleLinkUp: Port 2: Link up: 1-Gbps Full-Duplex
MAC Port 2: link up
cpsw-3g: MAC port addr: 70:ff:76:1f:60:3e

Enet L2 cpsw Menu:
 's'  -  Print statistics
 'r'  -  Reset statistics
 'm'  -  Show allocated MAC addresses
 'x'  -  Stop the test

s

Print statistics
----------------------------------------------

 cpsw-3g - Port 2 statistics
--------------------------------

I verified SW14/15/16 on the ControlCard are all in the default 'OFF' position which should route CPSW RGMII2 to the onboard PHY.

Any ideas?

over 1 year ago

0 Shaunak Deshpande over 1 year ago

TI__Genius 16402 points

Hi Steven,

I'll try to replicate the same on my end and get back to you with some update by tomorrow.

Regards,

Shaunak

0 Shaunak Deshpande over 1 year ago in reply to Shaunak Deshpande

TI__Genius 16402 points

Hi Steven,

When you try to print the statistics, you don't see any port stats correct? Can you please help me verify if you see some prints like the one in the screenshot attached.

Regards,

Shaunak

0 Shaunak Deshpande over 1 year ago in reply to Shaunak Deshpande

TI__Genius 16402 points

Hi Steven,

Update on Replicating the issue:

I tried to replicate the scenario with the same device, SDK Version, Boot mode and all the configurations mentioned above.I

Test setup:

Used ColaSoft packet builder (Windows OS), and sent 5000 ARP packets with source MAC as 00:00:00:00:00:00, destination MAC as what is displayed in the application logs for your AM263Px-CC device.
On printing the statistics in the application, I was able to see the 5000 packets received and transmitted back successfully. Attaching the screenshot below:
Port stats before flooding ARP packets:

Port stats after flooding ARP packets:
Wrieshark Capture:

Packet from PC to AM263Px-CC:

Packet from AM263Px-CC to PC:

In case you see the "s" prompt not printing statistics, can you please try entering "r" (reset statistics) and try printing the stats again?

Please let me know if I can help with anything else.

Regards,

Shaunak

0 Steven Hansen over 1 year ago in reply to Shaunak Deshpande

Intellectual 666 points

Hi Shaunak,

I've tried resetting statistics with "r", but "s" still prints nothing. In the code I see the print function skips any registers that are zero. Looking at the CPSW registers with the memory browser I see the CPSW statistics registers are all zero, which explains why I'm not seeing a printout. But obviously I'm not sure why the statistics are all zero.

Reset + Print:

==========================
     Layer 2 CPSW Test    
==========================

Init all peripheral clocks
----------------------------------------------

Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task

Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 

Init all configs
----------------------------------------------
cpsw-3g: init config
cpsw-3g: Open port 2
EnetPhy_bindDriver:1828 
PHY 0 is alive

Attach core id 0 on all peripherals
----------------------------------------------
cpsw-3g: Attach core
cpsw-3g: Open DMA
initQs() txFreePktInfoQ initialized with 16 pkts
cpsw-3g: Waiting for link up...
Cpsw_handleLinkUp:1629 
MAC Port 2: link up
cpsw-3g: MAC port addr: 70:ff:76:1f:60:3e

Enet L2 cpsw Menu:
 's'  -  Print statistics
 'r'  -  Reset statistics
 'm'  -  Show allocated MAC addresses
 'x'  -  Stop the test

s

Print statistics
----------------------------------------------

 cpsw-3g - Port 2 statistics
--------------------------------

r

Reset statistics
----------------------------------------------
cpsw-3g: Reset statistics
s

Print statistics
----------------------------------------------

 cpsw-3g - Port 2 statistics
--------------------------------

Wireshark capture:

Output from CCS -> Scripts -> CPSW Print Reg -> cpsw_main_print_reg:

Cortex_R5_0: GEL Output: ------------------------------------
Cortex_R5_0: GEL Output:  CPSW 
Cortex_R5_0: GEL Output: ------------------------------------
Cortex_R5_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA01903
Cortex_R5_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
Cortex_R5_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x00000000
Cortex_R5_0: GEL Output: SGMII_MODE_REG                 = 0x00000000
Cortex_R5_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
Cortex_R5_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
Cortex_R5_0: GEL Output: SGMII_IDVER_REG                = 0x00000000
Cortex_R5_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x00000000
Cortex_R5_0: GEL Output: STATUS_REG                     = 0x00000000
Cortex_R5_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
Cortex_R5_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
Cortex_R5_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
Cortex_R5_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
Cortex_R5_0: GEL Output: TX_CFG_REG                     = 0x00000000
Cortex_R5_0: GEL Output: RX_CFG_REG                     = 0x00000000
Cortex_R5_0: GEL Output: AUX_CFG_REG                    = 0x00000000
Cortex_R5_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
Cortex_R5_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
Cortex_R5_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
Cortex_R5_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x41000059
Cortex_R5_0: GEL Output: ALIVE_REG                      = 0x00000001
Cortex_R5_0: GEL Output: LINK_REG                       = 0x00000001
Cortex_R5_0: GEL Output: LINK_INT_RAW_REG               = 0x00000003
Cortex_R5_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
Cortex_R5_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
Cortex_R5_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
Cortex_R5_0: GEL Output: USER_INT_RAW_REG               = 0x00000001
Cortex_R5_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
Cortex_R5_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
Cortex_R5_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
Cortex_R5_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
Cortex_R5_0: GEL Output: POLL_REG                       = 0x00000064
Cortex_R5_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
Cortex_R5_0: GEL Output: CLAUS45_REG                    = 0x00000000
Cortex_R5_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
Cortex_R5_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
Cortex_R5_0: GEL Output: USER_ACCESS_REG_0              = 0x2020796D
Cortex_R5_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
Cortex_R5_0: GEL Output: ------------------------------------
Cortex_R5_0: GEL Output: REVISION                       = 0x00000000
Cortex_R5_0: GEL Output: control                        = 0x00000000
Cortex_R5_0: GEL Output: EOI_REG                        = 0x00000000
Cortex_R5_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
Cortex_R5_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
Cortex_R5_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
Cortex_R5_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
Cortex_R5_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
Cortex_R5_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
Cortex_R5_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
Cortex_R5_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
Cortex_R5_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
Cortex_R5_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
Cortex_R5_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
Cortex_R5_0: GEL Output: ------------------------------------
Cortex_R5_0: GEL Output: CPSW_ID_VER_REG                = 0x6B901103
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x0004E004
Cortex_R5_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
Cortex_R5_0: GEL Output: STAT_PORT_EN_REG               = 0x00000007
Cortex_R5_0: GEL Output: PTYPE_REG                      = 0x00000002
Cortex_R5_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
Cortex_R5_0: GEL Output: THRU_RATE_REG                  = 0x00003001
Cortex_R5_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
Cortex_R5_0: GEL Output: TX_START_WDS_REG               = 0x00000008
Cortex_R5_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
Cortex_R5_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
Cortex_R5_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
Cortex_R5_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
Cortex_R5_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
Cortex_R5_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
Cortex_R5_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
Cortex_R5_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
Cortex_R5_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
Cortex_R5_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
Cortex_R5_0: GEL Output: P0_CONTROL_REG                 = 0x0002000B
Cortex_R5_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
Cortex_R5_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
Cortex_R5_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
Cortex_R5_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
Cortex_R5_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
Cortex_R5_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
Cortex_R5_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
Cortex_R5_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
Cortex_R5_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
Cortex_R5_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
Cortex_R5_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
Cortex_R5_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
Cortex_R5_0: GEL Output: P0_RX_GAP_REG                  = 0x00000000
Cortex_R5_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
Cortex_R5_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
Cortex_R5_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
Cortex_R5_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
Cortex_R5_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
Cortex_R5_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
Cortex_R5_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
Cortex_R5_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
Cortex_R5_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
Cortex_R5_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
Cortex_R5_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
Cortex_R5_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
Cortex_R5_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
Cortex_R5_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
Cortex_R5_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
Cortex_R5_0: GEL Output: PN_RESERVED_REG                = 0x00000000
Cortex_R5_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
Cortex_R5_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
Cortex_R5_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
Cortex_R5_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
Cortex_R5_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
Cortex_R5_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
Cortex_R5_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
Cortex_R5_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
Cortex_R5_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000000
Cortex_R5_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
Cortex_R5_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
Cortex_R5_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
Cortex_R5_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
Cortex_R5_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
Cortex_R5_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
Cortex_R5_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
Cortex_R5_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
Cortex_R5_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
Cortex_R5_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
Cortex_R5_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
Cortex_R5_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
Cortex_R5_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
Cortex_R5_0: GEL Output: PN_SA_L_REG                    = 0x00000000
Cortex_R5_0: GEL Output: PN_SA_H_REG                    = 0x00000000
Cortex_R5_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
Cortex_R5_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
Cortex_R5_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
Cortex_R5_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
Cortex_R5_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
Cortex_R5_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_STATUS_REG              = 0xD0000000
Cortex_R5_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x00DD0000
Cortex_R5_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
Cortex_R5_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
Cortex_R5_0: GEL Output: FETCH_LOG_y (skipped)
Cortex_R5_0: GEL Output: ------------------------------------
Cortex_R5_0: GEL Output: RXGOODFRAMES                   = 0x00000000
Cortex_R5_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXCRCERRORS                    = 0x00000000
Cortex_R5_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
Cortex_R5_0: GEL Output: RXFRAGMENTS                    = 0x00000000
Cortex_R5_0: GEL Output: ALE_DROP                       = 0x00000000
Cortex_R5_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
Cortex_R5_0: GEL Output: RXOCTETS                       = 0x00000000
Cortex_R5_0: GEL Output: TXGOODFRAMES                   = 0x00000000
Cortex_R5_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: TXOCTETS                       = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES64                  = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
Cortex_R5_0: GEL Output: NETOCTETS                      = 0x00000000
Cortex_R5_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
Cortex_R5_0: GEL Output: PORTMASK_DROP                  = 0x00000000
Cortex_R5_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
Cortex_R5_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
Cortex_R5_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
Cortex_R5_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
Cortex_R5_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
Cortex_R5_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
Cortex_R5_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
Cortex_R5_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
Cortex_R5_0: GEL Output: RXGOODFRAMES                   = 0x00000000
Cortex_R5_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
Cortex_R5_0: GEL Output: RXCRCERRORS                    = 0x00000000
Cortex_R5_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
Cortex_R5_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
Cortex_R5_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
Cortex_R5_0: GEL Output: RXFRAGMENTS                    = 0x00000000
Cortex_R5_0: GEL Output: ALE_DROP                       = 0x00000000
Cortex_R5_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
Cortex_R5_0: GEL Output: RXOCTETS                       = 0x00000000
Cortex_R5_0: GEL Output: TXGOODFRAMES                   = 0x00000000
Cortex_R5_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
Cortex_R5_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
Cortex_R5_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
Cortex_R5_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
Cortex_R5_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
Cortex_R5_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
Cortex_R5_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
Cortex_R5_0: GEL Output: RXIPGERROR                     = 0x00000000
Cortex_R5_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
Cortex_R5_0: GEL Output: TXOCTETS                       = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES64                  = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
Cortex_R5_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
Cortex_R5_0: GEL Output: NETOCTETS                      = 0x00000000
Cortex_R5_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
Cortex_R5_0: GEL Output: PORTMASK_DROP                  = 0x00000000
Cortex_R5_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
Cortex_R5_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
Cortex_R5_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
Cortex_R5_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
Cortex_R5_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
Cortex_R5_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
Cortex_R5_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
Cortex_R5_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
Cortex_R5_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
Cortex_R5_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
Cortex_R5_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
Cortex_R5_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
Cortex_R5_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
Cortex_R5_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
Cortex_R5_0: GEL Output: IDVER_REG                      = 0x4E8A010C
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x00020025
Cortex_R5_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
Cortex_R5_0: GEL Output: TS_PUSH_REG                    = 0x00000000
Cortex_R5_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
Cortex_R5_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
Cortex_R5_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
Cortex_R5_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
Cortex_R5_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
Cortex_R5_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
Cortex_R5_0: GEL Output: INT_ENABLE_REG                 = 0x00000001
Cortex_R5_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
Cortex_R5_0: GEL Output: EVENT_POP_REG                  = 0x00000000
Cortex_R5_0: GEL Output: EVENT_0_REG                    = 0x00000000
Cortex_R5_0: GEL Output: EVENT_1_REG                    = 0x00000000
Cortex_R5_0: GEL Output: EVENT_2_REG                    = 0x00000000
Cortex_R5_0: GEL Output: EVENT_3_REG                    = 0x00000000
Cortex_R5_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
Cortex_R5_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
Cortex_R5_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000004
Cortex_R5_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
Cortex_R5_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
Cortex_R5_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
Cortex_R5_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
Cortex_R5_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
Cortex_R5_0: GEL Output: CONTROL_REG_l                  = 0x00000000
Cortex_R5_0: GEL Output: LENGTH_REG_l                   = 0x00000000
Cortex_R5_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
Cortex_R5_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
Cortex_R5_0: GEL Output: NUDGE_REG_l                    = 0x00000000
Cortex_R5_0: GEL Output: COMP_LOW_REG                   = 0x00000000
Cortex_R5_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x00000000
Cortex_R5_0: GEL Output: LENGTH_REG                     = 0x00000000
Cortex_R5_0: GEL Output: PPM_LOW_REG                    = 0x00000000
Cortex_R5_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
Cortex_R5_0: GEL Output: NUDGE_REG                      = 0x00000000
Cortex_R5_0: GEL Output: IDVER_REG                      = 0x00290105
Cortex_R5_0: GEL Output: STATUS_REG                     = 0x80000400
Cortex_R5_0: GEL Output: CONTROL_REG                    = 0x800000C0
Cortex_R5_0: GEL Output: CONTROL2_REG                   = 0x00000000
Cortex_R5_0: GEL Output: PRESCALE_REG                   = 0x0003D090
Cortex_R5_0: GEL Output: AGING_TIMER_REG                = 0x000000C9
Cortex_R5_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
Cortex_R5_0: GEL Output: TABLE_WORD2_REG                = 0x00000001
Cortex_R5_0: GEL Output: TABLE_WORD1_REG                = 0x100070FF
Cortex_R5_0: GEL Output: TABLE_WORD0_REG                = 0x761F603E
Cortex_R5_0: GEL Output: PORT_CONTROL_REG_y             = 0x00001003
Cortex_R5_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000007
Cortex_R5_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000007
Cortex_R5_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000007
Cortex_R5_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
Cortex_R5_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
Cortex_R5_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
Cortex_R5_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
Cortex_R5_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
Cortex_R5_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
Cortex_R5_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
Cortex_R5_0: GEL Output: POLICER_PIR_REG                = 0x00000000
Cortex_R5_0: GEL Output: POLICER_CIR_REG                = 0x00000000
Cortex_R5_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
Cortex_R5_0: GEL Output: POLICER_CTL_REG                = 0x80000000
Cortex_R5_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
Cortex_R5_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
Cortex_R5_0: GEL Output: THREAD_DEF_REG                 = 0x00008000
Cortex_R5_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
Cortex_R5_0: GEL Output: THREAD_VAL_REG                 = 0x00000000

0 Steven Hansen over 1 year ago in reply to Steven Hansen

Intellectual 666 points

I do see both lights on the RJ45 connector on the ControlCard. The left light is amber (1000BASE-T) and the right light flashes green when I send a packet. This seems like some kind of software config. issue, but I'm not finding any obvious cause.

0 Steven Hansen over 1 year ago in reply to Steven Hansen

Intellectual 666 points

Output from Scripts -> CPSW Statistics Print -> cpsw_3g_statsprint_nonzero (after running example and sending packets):

Cortex_R5_0: GEL Output:           STATS          
Cortex_R5_0: GEL Output: --------------------------------
Cortex_R5_0: GEL Output:           PORT0 STATS          
Cortex_R5_0: GEL Output: --------------------------------
Cortex_R5_0: GEL Output: --------------------------------
Cortex_R5_0: GEL Output:           PORT1 STATS          
Cortex_R5_0: GEL Output: --------------------------------
Cortex_R5_0: GEL Output: --------------------------------
Cortex_R5_0: GEL Output:           PORT2 STATS          
Cortex_R5_0: GEL Output: --------------------------------

0 Steven Hansen over 1 year ago in reply to Steven Hansen

Intellectual 666 points

Finally figured it out. SW15 on the ControlCard was in the wrong position.

It seems SW15 was installed in the opposite orientation of SW14 and SW16. This means that SW14/16 had to be in the "down" position (off), but SW15 has to be in the "UP" position (off).

Now getting statistics as expected:

==========================
     Layer 2 CPSW Test    
==========================

Init all peripheral clocks
----------------------------------------------

Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task

Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 

Init all configs
----------------------------------------------
cpsw-3g: init config
cpsw-3g: Open port 2
EnetPhy_bindDriver:1828 
PHY 0 is alive

Attach core id 0 on all peripherals
----------------------------------------------
cpsw-3g: Attach core
cpsw-3g: Open DMA
initQs() txFreePktInfoQ initialized with 16 pkts
cpsw-3g: Waiting for link up...
Cpsw_handleLinkUp:1629 
MAC Port 2: link up
cpsw-3g: MAC port addr: 70:ff:76:1f:60:3e

Enet L2 cpsw Menu:
 's'  -  Print statistics
 'r'  -  Reset statistics
 'm'  -  Show allocated MAC addresses
 'x'  -  Stop the test

s

Print statistics
----------------------------------------------
  rxGoodFrames            = 328
  rxOctets                = 35460
  txGoodFrames            = 328
  txBcastFrames           = 19
  txMcastFrames           = 305
  txOctets                = 35460
  octetsFrames64          = 122
  octetsFrames65to127     = 394
  octetsFrames128to255    = 128
  octetsFrames256to511    = 12
  netOctets               = 70920
  txPri[0]                = 328
  txPriBcnt[0]            = 35460

 cpsw-3g - Port 2 statistics
--------------------------------
  rxGoodFrames            = 328
  rxBcastFrames           = 19
  rxMcastFrames           = 305
  rxOctets                = 35460
  txGoodFrames            = 328
  txOctets                = 35460
  octetsFrames64          = 122
  octetsFrames65to127     = 394
  octetsFrames128to255    = 128
  octetsFrames256to511    = 12
  netOctets               = 70920
  aleUnknownUcast         = 1
  aleUnknownUcastBcnt     = 64
  aleUnknownBcast         = 1
  aleUnknownBcastBcnt     = 346
  txPri[0]                = 328
  txPriBcnt[0]            = 35460

Arm-based microcontrollers

Arm-based microcontrollers forum

AM263P4: Problems with L2 CPSW example in SDK