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PBIST module questions [urgent]

Other Parts Discussed in Thread: HALCOGEN

 

In TRM "Literature Number: SPNU489B", PBIST chapter, in table 6-1, i have the following questions:
1. What is ESRAM ? Is it the 160KB SRAM (address: 0x0800 0000-0x0822 7FFF) ?
2.
what is sigle/two port RAM? what does sigle/two mean ?

3. how to use the RGS/RDS value ? In the table 6-1,in RGS/RDS column,  "5/0..5" and "1/0..2", what does it mean ?
And other questions continue,
4. In many registers, e.g., in FSRF0 and FSRF1, it metions port 0 and port 1, what is port 0 and port 1 ? does it have any relationship with single/dual port ?
5. what should do in these two function "memoryPort0TestFailNotification" and "memoryPort1TestFailNotification"? these two function are called in assembly language "_memoryTest_", which is generated by HALCoGen and called in function "_c_int00()".
6. how to test PBIST functionality ? how to make it fail ? which errors will cause PBIST test fail ?
7. Besides TRM document, Is there any other documents describe PBIST module? can you send to me?
 
thanks very much.
  • Fumin Li said:

     

     

    In TRM "Literature Number: SPNU489B", PBIST chapter, in table 6-1, i have the following questions:
    1. What is ESRAM ? Is it the 160KB SRAM (address: 0x0800 0000-0x0822 7FFF) ?
    HW: Yes
    2.
    what is sigle/two port RAM? what does sigle/two mean ?
    HW: single port RAM can only be accessed by one master at one time. Dual port RAM can be access by two masters at the same time. For example, if both DMA and CPU wants to access 160K SRAM, one of them has to wait. If both ADC and CPU wants to access the ADC RAM, they can do it together (one read, one write).
    3. how to use the RGS/RDS value ? In the table 6-1,in RGS/RDS column,  "5/0..5" and "1/0..2", what does it mean ?
    HW: It is a unique ID to trace to the damaged RAM once an error is found. 5/0..5 means RGS=5, RDS=0,1,..or 5. RGS is the group number. Your application should assign this number to RINFOL to test the target RAM. In additional, RDS divides this group into several test regions. You don't need to touch RDS unless a failure occurs.

    And other questions continue,
    4. In many registers, e.g., in FSRF0 and FSRF1, it metions port 0 and port 1, what is port 0 and port 1 ? does it have any relationship with single/dual port ?
    HW: I am not sure. I need to check with the designer and get back to you.
    HW: Here is the feedback from designer. We test our RAM us 64 bit width bus, calling 32 bit as one port. So, we have two ports.
    5. what should do in these two function "memoryPort0TestFailNotification" and "memoryPort1TestFailNotification"? these two function are called in assembly language "_memoryTest_", which is generated by HALCoGen and called in function "_c_int00()".
    HW: If there is error in RAM test, mostly like, this means the IC is broken. I recommend you return the IC to TI to do failure analysis.
    6. how to test PBIST functionality ? how to make it fail ? which errors will cause PBIST test fail ?

    HW: I don't think you can inject a error. You can make it fail by testing an non-existing algrithm on a certain RAM. For example, test triple_read_slow_read on SRAM.

    7. Besides TRM document, Is there any other documents describe PBIST module? can you send to me?
     HW: I will send you through email.
    thanks very much.