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AM2634: Output XBAR - flag force controls the output directly

Viacheslav Potapov
Prodigy 10 points
Part Number: AM2634

Hello, could you help me with the Output XBAR, please?

While testing I have found one strange behavior of the OUTPUTXBAR.
When the OUTPUTLATCH is used (OUTPUTXBAR_OUTLATCH.bit0 = 1) and there are no inputs for OUTPUTXBAR:

  1. setting OUTPUTXBAR_FLAGFORCE to 1 sets the OUT to 1 (XBAROUT0 pin is 1), but the STATUS is still 0 (while the FLAG is 1)
  2. setting OUTPUTXBAR_FLAGFORCE to 0 sets the OUT to 0 (XBAROUT0 pin is 0), but the FLAG is still 1
  3. setting OUTPUTXBAR_FLAG_CLR to 1 clears the FLAG, so both are 0
  4. when I do the step 1) first and the step 3) after, the FLAG is reset, the STATUS is still 0, but OUT is 1 (XBAROUT0 pin is 1)

When the OUTPUTXBAR_OUTLATCH.bit0 = 0, the FORCE doesn't affect on the pin.

When I connect CMPSS output directly, setting its output to 1 sets the OUT to 1, setting to 0 - OUT is 0.
But when I connect CMPSS output via OUTPUTXBAR LATCH, it actually doesn't latch the output (while FLAG is latched, but at the same time STATUS reflect correct OUT state).

Could you please explain how the OUTPUTXBAR FORCE and LATCH mechanisms work?
And why the pin physical status changed, but the STATUS register not (when LATCH is used and there are no inputs for OUTPUTXBAR)? Why the FORCE directly controls the pin?
Especially, why the LATCH doesn't work? 

The pin is configured for XBAROUT0 (mux mode = 5, dir = out). All inversions disabled.

All these steps I have done manually in CCS and the same I have implemented in the code, but behavior is the same.

Also, why there is no description for many registers in the AM263x Register Addendum? Especially for XBARs!

Thank you.

Pictures that describe the test:











  • 0
    TI__Mastermind 20122 points

    Hello Viacheslav,

    One key issue here is that the OUTPUTXBAR output signal should not be used without a designated input signal also configured. Without an input driving the OUTPUTXBAR block, the output signal will be unpredictable. The floating input will be subject to influence from various signals in close proximity (including the FLAG, LATCH, and FORCE control signals). My recommendation would be to retry these experiments with a simple defined input signal (High or Low is up to you). When the input requirement condition is met, the status and logical functionality built around the OUTPUTXBAR operates as expected and portrayed in the diagram below from the TRM.

    Hope this information helps get you moving forward. Please reach out with additional questions as needed.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 10 points

    Hello Zackary,

    thank you for your answer. This explains my question, especially the picture you sent.

    Where can I find this picture? This one is much better than what we have in TRM (Rev.E - https://www.ti.com/lit/pdf/spruj17)

    But I still have some questions regarding the OUTPUTXBAR:

    • I have tried to connect CMPSSAH/L outputs to PWM XBAR and to OUTPUTXBAR, so it goes a PWM trip and it changes signal on output XBAR pin. But when I invert output signal (OUTPUTXBar_OutInvert set to 1) the output signal is inverted, but the STATUS does not (OUTPUTXBar_Status register reflects an actual status on the input signal to OUTPUTXBAR, if CMPSS output 1 - the STATUS is 1 even if output signal is inverted). On the new OUTPUTXBAR picture, the STATUS is read directly after Sync, but all names are PWM, is it a typo? Do we read STATUS after Sync, so it reflect an input status and no output, right?
    • Another question. With the same input (CMPSSAH/L), when I use LATCH, when the CMPSS output goes from 1 to 0, the output signal is not latched and it also goes to 0, but should stay at 1 until I clear it (OUTPUTXBar_Flag_CLR set to 1), shouldn't?

    Please, if you have updated TRM, could you share it?

    Thank you.

    Best regards,
    Viacheslav Potapov

  • +1 in reply to Viacheslav Potapov
    TI__Mastermind 20122 points

    Hello Viacheslav,

    Thank you for pointing this out, the diagram will be included in the next release of SPRUJ17. I would expect this release sometime in February, but will notify you when it available.

    1) "OUTPUTXBar_Status register reflects an actual status on the input signal to OUTPUTXBAR, if CMPSS output 1 - the STATUS is 1 even if output signal is inverted" This statement is correct and working as expected. The OutInvert is only meant to control the polarity of the signal at XBAROUT.Out pin, not the polarity of the input status register bit.

    2) The "LATCH" mechanism here should still reflect the value of the CMPSS output, the signal is just synchronized now with the 200 MHz clock.The Flag_CLR and FLAG_FRC controls can be used as a way to override the latched value.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 10 points

    Hello Zackary, I expect that the latch will actually latch the input to output xbar, so if CMPSS goes back to 0 the value 1 is still latched, otherwise why it is called latch?

    Thank you for the support.

     

  • 0 in reply to Viacheslav Potapov
    TI__Mastermind 20122 points

    You are correct, the latch is always storing the clock synchronized input signal. The output of the xbar will only reflect the latched input value when the OUTLATCH.LATCH_SEL bit is set. The flag bit will always reflect the latched value which as I mentioned previously can be purposefully overridden with the Flag_CLR and FLAG_FRC control bits. Does this address your concern?

    Best Regards,

    Zackary Fleenor