Other Parts Discussed in Thread: , SYSCONFIG
Hello,
I would like to present you some problem regarding the UART TX DMA data getting corrupted while running the CPU/MCLK clocks above 32MHz. I had problems on my custom hardware and firmware project that I am currently working on but was able to narrow it down to what seems to be problems in the clocking domain of the microcontroller. For that, I was able to reliably reproduce the faulty behaviour on a LP-MSPM0G3507 launchpad (marked Rev. A) and having the UART TX DMA example ("uart_tx_multibyte_fifo_dma_interrupts_LP_MSPM0G3507_nortos_ticlang") provided by TI only slightly modified so that it busywaits on EOT and DMADONE flags repetitively and outputs an array of ASCII characters (that is not being changed) in an infinite while loop on 115200baud.
The example uses a CPU/MCLK/ULPCLK directly provided by the SYSOSC and everything works flawlessly. When I provide those clocks from the SYSPLL but CPUCLK=MCLK=ULPCLK=32MHz everything works still without problems. It also works if I change up the UDIV so that ULPCLK=MCLK/2=16MHz without data corruption. If I now try to clock CPUCLK/MCLK any higher than 32MHz I start running into problems with the data received on the PC side being corrupted.
It looks to me that if MCLK >32MHz data will get corrupted in those cases where MCLK != ULPCLK. If for example I clock MCLK=40MHz and ULPCLK=40MHz (UDIV=/1) then everything still works without corruption. If I now change the UDIV to /2 and ULPCLK=MCLK/2=20MHz I start to see corruption. This also happens for example if I try (like in my real project that I am working on) to clock the MCLK=80MHz and ULPCLK=40MHz. It looks to me that at the moment this will limit the total usable CPUCLK/MCLK to max. 40MHz without seeing corruptions because ULPCLK_max is 40MHz.
I have also tried to supply a different clocking source to the UART0 peripheral (MFCLK=4MHz) while keeping MCLK clock speeds way up. This also still leads to corruptions on the received TX data.
As I mentioned I changed up the provided UART TX DMA example for this purposes while keeping track via git over the changes and fault introducing configuration states that I have written about in this text, so that you can backtrack my changes, diff the commits and easily bring the MSP into those faulty data corrupting states that I have described.
Edit: In my real project with 80MHz clocks the UART data does not get corrupted if I use blocking UART writing, so I assume that the problem is with the DMA clocking.
Every bit of help and information on this matter is highly appreciated and thanks in advance
Jonas
uart_tx_multibyte_fifo_dma_interrupts_LP_MSPM0G3507_nortos_ticlang-DATA-CORRUPTION.tar.gz