MCU-PLUS-SDK-AM263X: Definition of CSL_EPWM_AQCTLA and others

I am trying to understand ePWM registers.  There is a Register Addendum manual (spruj42d.pdf) that gives a definition for the AQCTL register, associated with a memory offset of 0x20 (Table 3-704).  In the SDK, this is defined in the file cslr_etpwm.h as follows:

#define CSL_EPWM_AQCTL                                                         (0x00000020U)

My question is what about the later registers, defined in this same file as:

#define CSL_EPWM_AQCTLA                                                        (0x00000080U)
#define CSL_EPWM_AQCTLA2                                                       (0x00000082U)
#define CSL_EPWM_AQCTLB                                                        (0x00000084U)
#define CSL_EPWM_AQCTLB2                                                       (0x00000086U)

What is their definition? 

I ask because I have received some code that is setting the location (CONFIG_EPWM0_BASE_ADDR+CSL_EPWM_AQCTLA+2) to values such as

And some of these are setting what would be reserved bits or bits that only matter if SHDWAQxMODE is set to 1 while setting SHDWAQxMODE to 0.