TMDSCNCD263P: ENET Examples: PHY Loopback Example Failure

Hi Kier,

Initially the IP address will be shown as 0.0.0.0 when the netif is initialized in the application (before the board gets an IP through DHCP). As you can notice in my case I got IP assigned after 15 seconds, my DHCP server took a bit long to assign an IP.

I tried running MCU_PLUS_SDK 09_01_00_20 enet_lwip_cpsw example on TMDSCNCD263P Proc E2 board. I was able to get the IP address. I also was able to ping the board

Attaching my logs below:

==========================
      ENET LWIP App       
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
Link Status Changed. PHY: 0x0, state: up
EnetPhy_bindDriver:1828 
PHY 0 is alive
Starting lwIP, local interface IP is dhcp-enabled
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1e:5e:df
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
Cpsw_handleLinkUp:1629 
MAC Port 2: link up
link_callback==UP
      5. 44s : CPU load =   1.20 %
     10. 44s : CPU load =   1.00 %
     15. 44s : CPU load =   0.99 %
[0]status_callback==UP, local interface IP is 172.24.227.239
     20. 44s : CPU load =   1.01 %
     25. 44s : CPU load =   1.01 %

Now, in your case, my suspicion is around 2 things:

1. Your board revision number. Can you please share your PCB#? Is it E1 or E2?

2. Can you ensure the DHCP server is working fine? Since the out-of-box example is working fine without any modifications required, the next thing in picture is the DHCP server which might not be working as expected.

Regards,

Shaunak

Hi Shaunak,

Many thanks for checking.

1. I have no sticker in that position but on the other side next to the HSEC, it says PROC159E2(001). What is your suspicion?

2. I am quite sure DHCP works because, as I mentioned, my oscilloscope was using the same cable and it was allocated an IP address automatically.

Yesterday's test was done at home. I tested again today in the office with the same results. This time I waited until the software hit an assert:

==========================
      ENET LWIP App       
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
Link Status Changed. PHY: 0x0, state: up
EnetPhy_bindDriver:1828 
PHY 0 is alive
Starting lwIP, local interface IP is dhcp-enabled
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1f:60:20
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
Cpsw_handleLinkUp:1629 
MAC Port 2: link up
link_callback==UP
      5. 44s : CPU load =   1.17 %
     10. 44s : CPU load =   0.97 %
     15. 44s : CPU load =   1.04 %
     20. 44s : CPU load =   1.05 %
     25. 44s : CPU load =   1.07 %
     30. 44s : CPU load =   1.04 %
     35. 44s : CPU load =   1.03 %
     40. 44s : CPU load =   1.17 %
     45. 44s : CPU load =   1.15 %
     50. 44s : CPU load =   1.08 %
     55. 44s : CPU load =   1.10 %
     60. 44s : CPU load =   1.04 %
     65. 44s : CPU load =   1.04 %
     70. 44s : CPU load =   1.05 %
     75. 44s : CPU load =   1.04 %
     80. 44s : CPU load =   1.02 %
     85. 44s : CPU load =   1.03 %
     90. 44s : CPU load =   1.11 %
     95. 44s : CPU load =   1.14 %
    100. 44s : CPU load =   1.10 %
    105. 44s : CPU load =   1.10 %
    110. 44s : CPU load =   1.08 %
    115. 44s : CPU load =   1.05 %
    120. 44s : CPU load =   1.04 %
    125. 44s : CPU load =   1.06 %
delete meASSERT: 126.668921s: /nightlybuilds/mcupsdk_internal/jenkins/mcu_plus_sdk_am263px_09_01_00_20/source/networking/lwip/lwip-stack/src/core/inet_chksum.c:inet_cksum_pseudo_partial_base:416: 0 failed !!!

What can I try next for diagnosis please?

Hi Kier,

1. There was an issue with MDIO on PROC E1 revision boards. Since yours is E2, we're safe here

2. Got it. Just wanted to be sure about it

Can you please do the below experiment and let me know what you see?

1. Can you run the Out-of-box CPSW loopback example, print the stats and verify if the Rx and Tx are working as expected? Can you please try this with NO boot mode? 

software-dl.ti.com/.../EVM_SETUP_PAGE.html

2. Are you using CCS to build the project and load the file? If yes, what is the CCS version. I recommend using CCS 12.5 with SDK v09.01.

Regards,

Shaunak

Hi Shaunak,

Thank you.

1.Here's my results:

MAC Loopback (All tests passed)

 
 0: Internal MAC loopback 
 1: External PHY loopback 
 
 Enter option: 0
=============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1655 
Test complete: PASS
=============================
 Enet Loopback: Iteration 2 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1655 
Test complete: PASS
=============================
 Enet Loopback: Iteration 3 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1655 
Test complete: PASS
=============================
 Enet Loopback: Iteration 4 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1655 
Test complete: PASS
=============================
 Enet Loopback: Iteration 5 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 1 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown:1655 
Test complete: PASS
Loopback application completed
All tests have passed!!

PHY Loopback (This second test doesn't indicate any pass or failure. Does this indicate some cause?)

 0: Internal MAC loopback 
 1: External PHY loopback 
 
 Enter option: 1
=============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
EnetPhy_bindDriver:1828 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp:1629 

2. I'm using CCS12.5 with mcu_plus_sdk_am263px_09_01_00_20. I used DevBoot mode. BTW, I think the picture caption "NO BOOT MODE" is mislabelled. 

Hi Kier,

1. What is the syscfg version you are using? It should ideally be 1.18

MAC loopback test result seems fine but I see an issue with your PHY loopback test results

The test should PASS with an output as shown here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM263PX/latest/exports/docs/api_guide_am263px/EXAMPLES_ENET_CPSW_LOOPBACK.html#autotoc_md1866

Kier, this seems to be some issue with the hardware setup. The out-of-box examples are working fine and I verified the enet_lwip_cpsw, enet_loopback examples on my end.

I would once recommend you to check the following:

1. Ensure correct sycfg version

2. Ensure correct power supply to the AM263Px device

3. Ensure correct hardware setup.

Can you please check the same and get back. Then we can discuss further.

Regards,
Shaunak

Hi Kier,

1. Can you please let me know the syscfg version of the examples used? There was some device data changes in the latest syscfg version.

2. Another thing you can try is loading your examples via SBL null boot mode and not via CCS? Let me know if you are unfamiliar with this. Will share the steps.

Regards,

Surbhi

Hi Shaunak,

1. The SysConfig version 1.18.0

2. I'm using USB-C power from a Thunderbolt dock. There's no indication that the power supply is no good.

3. For the loopback test, what hardware set-up should I check?

I tried my colleague's board. The results are the same:

 
 0: Internal MAC loopback 
 1: External PHY loopback 
 
 Enter option: 1
=============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2 
EnetPhy_bindDriver:1828 
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp:1629 

Here's a photo of my board. Are there any jumpers incorrectly placed?

Hi Surbhi,

1. The SysCfg version 1.18.0.

2. OK, I'll try booting using SBL but what is the theory here? Why would the boot source make any difference?

Hi Kier,

We have seen issues with loading AM263P board with the CCS gel files. The gel files were unable to set PLL clocks and hence RX clock, thats why no data was received. Flashing SBL null on the board and loading the app file after removing the CCS gel files helps.

Let me know if it helped.

Regards,

Surbhi

Hi Surbhi,

I'm having difficulty flashing the program to boot by SBL.

I set DEVBOOT mode, recycle the power then use UNIFLASH with the following files:

However, the flashing does not complete:

volume_downVerboseClearClose
[07/02/2024, 08:55:16] [INFO] Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: DevBoot mode
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000101
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000100
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Lockstep mode
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Lockstep mode
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 Reset DualCore ***
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: ***R5FSS1 Reset DualCore ***
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: PER PLL Configuration Complete
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling QSPI Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***
[07/02/2024, 08:55:17] [INFO] Cortex_R5_0: AM263Px
[07/02/2024, 08:55:18] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0
[07/02/2024, 08:55:39] [ERROR] Cortex_R5_0: Run failed...
[07/02/2024, 08:55:39] [ERROR] Cortex_R5_0: File Loader: Memory write failed: Timed out waiting for target to halt while executing am263px_flasher.out
[07/02/2024, 08:55:39] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0
[07/02/2024, 08:56:00] [ERROR] Cortex_R5_0: Run failed...

At the same time, I get "Failure to reset the Flash!! 0" in my Terminal window.

What am I doing wrong please?

Hi Kier,

Can you please change the device from AM263Px to AM263Px(SERIAL), change the boot mode to UART bootmode(SW6-> 1000). Load the sbl_null.release.tiimage.

In CCS double click on AM263px-cc target config, in advanced section, select Cortex_R5_0 and remove the csp gel file path is in the Initialization script field.

Reload the app binary and run it.

Regards,
Surbhi

Surbhi / Shaunak,

Can you confirm how you tested your enet PHY loopback please. Does it work in DevBoot? If so, then there's little point in my spending effort using SBL because the boot mode cannot be the cause.

Thank you.

Hi Kier,

It was tested in DEV bootmode before the release. It was also tested with SBL NULL flashed on the board and then sideloading the .out binary.

SBL might not be the issue but the gel scripts can be. There was an issue observed with Gel files incorrectly configuring the PLL clocks and thus the Rx clocks as mentioned by Surbhi. This seems to be an issue here as well since we saw the PHY loopback failing. 

Another quicker way to flash SBL NULL without using the UNIFLASH tool is:

1. Power off and Set the device in UART boot mode

2. In your SDK, open the tools/boot/  folder and launch your command prompt here

3. Use the command shared below to flash SBL NULL to your device (replace <xx> with the correct COM Port)

python uart_uniflash.py -p COM<xx> --cfg=sbl_prebuilt\am263px-cc\default_sbl_null.cfg

4. Power off and Set your device in OSPI boot mode. Power on.

5. In your CCS terminal, you should now see SBL NULL logs and once you connect to your core, load the .out binary application.

6. Run the PHY loopback test

Regards,

Shaunak