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Doze mode SCI wakeup?

Marco Moreno
Intellectual 300 points

Hi,

 

I have an application requirement to sleep ("doze") the TMS570 and wake up on a break condition on the SCI port.  It was my understanding that this could be done, but there are some slides I saw in this presentation:

http://processors.wiki.ti.com/images/0/0c/TMS570_MCU_1Day_Training_2011_Part1.pdf

that suggests otherwise.  In particular, slide 47 shows all clock domains are off except the HFO, Internal LFCLK, and RTI clock.  Back in the TMS570 data sheet, section 2.6.1, I found this in the sequence to enter Doze mode:

"Software writes to the clock domain disable register (CDDIS) to disable the GCLK (CPU clock), HCLK (system clock), VCLKP (peripheral VBUS clock), VCLK2 (peripheral VBUS clock2), VCLKA1(asynchronous peripheral VBUS clock1), and VCLKA2 (asynchronous peripheral VBUS clock2). All these domains must be disabled in order for the device to be in doze mode."

So, it sounds like if we don't actually turn off the clock to the SCI (VCLKP?) then we don't actually enter Doze mode.  There is some wording in section 13.7 for SCI low power mode that might be relevant, but I'm not sure.  If we put the SCI in low power mode, then shut VCLKP off to allow entering in to Doze mode, then will the micro wake on the break condition on the SCI?

 

Thanks,

Marco

 

  • 0
    TI__Genius 13810 points

    Yes. You have to turn off the VCLK to enter low power mode. This low power mode is a global low power mode, including SCI, CAN.... It is different from the low power mode bit in each peripheral. That bit only put individal peripheral into low power mode and you can change that bit any time you want. Once you enter the global low power mode, you have no VCLK/HCLK, no CCS access, can not re-flash the device...., you can only wake up the device through wake up interrupt.

    Suppose you use SCI as the wakeup interrupt and configure it well, once you send some message to SCI RX pin, the device will wakeup. The message itself might be lost since the wakeup take some time. The wake up interrupt is based on level and not on the clock edge. So, it does not require a clock.

    Be careful, if the wakeup interrupt is not configured well, once you enter low power mode, the device can not wakeup.

    Usually, when I debug the wakeup code, I leave a long loop (around 10s) before the device enters low power mode. Then, I can re-flash the device / connect to CCS in this long loop if the device can not wake up. Or you can switch the address between RAM and flash, and run code from RAM. Then, if the code cause sth bad, reset the device will go back to the flash.

    Regards,

    Haixiao

     

     

  • 0 in reply to Haixiao Weng
    Intellectual 300 points
    Mr. Weng, Thank you for the quick response. I'm looking for the specification for wake up timing in this scenario. In our protocol, we will use the low level on the SCI RX line to wake up the slave system and give it time enough to get up and running before sending any real information. This will happen very frequently, so we are concerned about the time it will take for the micro to come out of Doze mode. We are going to be using the port in non-LIN SCI mode. I see for LIN mode that there are some timing diagrams for wakeup, but I don't see any for non-LIN mode. Can you tell me how long the signal will need to be low before the micro will be able to wake up and service incoming data interrupts? Thanks, Marco
  • 0 in reply to Marco Moreno
    TI__Genius 13810 points

    I don't have such a timing diagram on my hand. It could be measured. In my mind, the most timing consuming thing is to bring the oscillator active (in ms) if it is turned off. The next one is to bring the LPO back to work. PLL also takes lots of time (a few thousands OSC clock) to re-lock. So, if you keep the PLL active during low-power mode, it will save lots of wakeup time. The cost is the power consumed by the PLL. It should be much lower than the current  consumed by the HCLK and VCLK.

    Regards,

    Haixiao