This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LP-AM243: 16-bit GPMC support in SysConfig

Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I have noticed that in the datasheet of AM243x it is mentioned that there is support for 16-bit memory in GPMC.

However when configuring the device in SysConfig, I am unable to select 16-bit and the only option is 8-bit.

See this picture below with SDK Version 9.1, CCS 12.3, SysConfig 18.0.

Thanks and regards

Manuel

  • Hi Manuel,

    The AM243x MCU+ SDK 09.00.00 only supports the GPMC NAND flash. The GPMC PSRAM will not be supported in AM243x MCU+ SDK 09.02.00 which is scheduled to be released in April 2024.

    Best regards,

    Ming

  • Hello Ming,

    please help me understand:

    What does NAND flash vs PSRAM has to do with the support for 16-bit memory in SysConfig?

    According to the datasheet, a 16- and 32-bit memory is supported by AM243x but these options are not available in SysConfig.

    Regards
    Manuel

  • Hi Manuel,

    Since the NAND flash only supports 8 bit data, so the syscfg only supports 8 bit data only. Here is the GPMC PSRAM example from AM263x MCU+ SDK 09.01.00, it only supports 16 bit data, because the PSRAM uses 16 bit data. 

    I know the AM243x GPMC supports both 16 and 8 bit data, but the GPMC driver does not support both at this moment. However, it will in 09.02.00.

    Best regards,

    Ming

  • Manuel

    Please feel free to open a new E2E, to see how best we can support your customer to move to GPMC 16 bit NAND, even if the current default SYSCFG only allows 8bit etc. 

  • Hello Manuel,

    I reopened the thread and assigned it on my name.

    Regards,

    Anil.

  • Hello Manuel,

    Please try to do the steps below to make 16bits operations 

    In the current MCU+SDK example, we support 8 bit.

    Currently, the 8 bit code is generated from system cfg. If possible please copy the entire generated code for GPMC to move to a new file.

    In the new file, you can add 8 more pin configurations for 16 bit operations.

    Below, one is configured from GPMC_AD8 to GPMC_AD15 as per the EVM SOC package .

    So, you need to update pins according to your LP Package.

    Next, change device type to 16bit and the remaining code should work for 16 bits as well.

    Please let me know if you are facing any issues.

    Regards,

    Anil.

        /* GPMC0_AD8 -> GPMC0_AD8 (V19) */
        {
            PIN_GPMC0_AD8,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD9 -> GPMC0_AD9 (T17) */
        {
            PIN_GPMC0_AD9,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD10 -> GPMC0_AD10 (R16) */
        {
            PIN_GPMC0_AD10,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD11 -> GPMC0_AD11 (W20) */
        {
            PIN_GPMC0_AD11,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD12 -> GPMC0_AD12 (W21) */
        {
            PIN_GPMC0_AD12,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD13 -> GPMC0_AD13 (V18) */
        {
            PIN_GPMC0_AD13,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD14 -> GPMC0_AD14 (Y21) */
        {
            PIN_GPMC0_AD14,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },
        /* GPMC0 pin config */
        /* GPMC0_AD15 -> GPMC0_AD15 (Y20) */
        {
            PIN_GPMC0_AD15,
            ( PIN_MODE(0) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
        },

    Regards,

    Anil.