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MSPM0L1306: SPI 32-bit frame with chip select glitch

Part Number: MSPM0L1306
Other Parts Discussed in Thread: TMAG5170-Q1,

We are interfacing the MSPM0L1306 via SPI with the TI hall effect magnetic sensor TMAG5170-Q1. This sensor requires a 32 bit frame, to achieve this we are pushing 2 packets (16 bits in each packet) into the FIFO and triggering at 50% level which is working fine on the data side. The issue here is that the chip select is getting de-asserted (set to HIGH) in between these 2 packets (shown in image and pointed by green arrow). The sensor is not accepting this frame.

Some configuration information here:

  • CTL0.SPH = FIRST
  • CTL0.SP0 = LOW
  • CTL0.FRF = MOTOROLA_4WIRE
  • CTL0.DSS = 16
  • IFLS.TXIFLSEL = 1/2 empty
  • CTL1.MSB = MSB first

Please advice on how this glitch can be avoided.