remove RX fifo flush when UART_read times out
The TI AM263 UART driver would clear RX fifo on timeout. We specify a timeout so that once a while we can breakout of UART read and feed watchdog. During this timeif any chars are received they were getting flushed by the TI driver.
Using TIMEOUT WAIT FOREVER or not flushing UART RX FIFO on timeout solves the issue.
The fix is in the TI driver
Consider putting this fix and adding a test for this scenario in the MCU+ SDK.
We use UART in interrupt mode, no DMA.
mcu_plus_sdk_am263x_09_00_00_35/source/drivers/uart/v0/uart_v0.c
| @@ -1011,12 +1009,23 @@ static Bool UART_readCancelNoCB(UART_Handle *handle, UART_Object *object, UART_A | ||
| /* Set size = 0 to prevent reading and restore interrupts. */ | ||
| object->readSizeRemaining = 0; | ||
| /* iontra.atlassian.net/.../PL-210 | ||
| * We dont flush the RX FIFO on timeout since otherwise, it will lose | ||
| * valid received characters | ||
| */ | ||
| #if 0 | ||
| { | ||
| uint8_t rdData; | ||
| uint32_t flag; | ||
| /* Flush the RX FIFO */ | ||
| do | ||
| { | ||
| flag = UART_getChar(attrs->baseAddr, &rdData); | ||
| } | ||
| while (flag != FALSE); | ||
| } | ||
| #endif |
