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MSPM0L1306: How to use the function of Forced Output(18.2.5.3)?

Kelly Li2
Prodigy 210 points
Part Number: MSPM0L1306
Other Parts Discussed in Thread: MSPM0G3507

I set TIMG4/PWM Channel 0/initial Value is High, and i hope that the PWM output keep Low after the PWM output is done.

i tried to make Forced Output enable, unfortunately i couldn't find this function in system configurations.

and i tried to set the register of TIMG4 directly, and i couldn't find the correctly register name.

TIMG4_CCACT_01[0] or TIMG4_CCACT_01 were both wrong.

Would you please kinldy let me know how to know the correct register name from MSPM0 L-Series Technical Reference Manual? (Question 1)

i just found the information about CCACT register from the follwoing section, but i don't know how to correspond to the specific TIMx.

for example, if we want to use these two register of TIMG4, What are their correct names? (Question 2)

And I use the following two lines of code to implement the functionality I need,  Is this the recommended method?  (Question 3)

            DL_TimerG_stopCounter(PWM_1_INST);
            DL_TimerG_setCaptureCompareOutCtl(PWM_1_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW,
            DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_FUNCVAL,
            DL_TIMERG_CAPTURE_COMPARE_0_INDEX);

many thanks.

  • 0
    TI__Mastermind 19877 points

    Hi, Kelly

    Kelly Li2 said:
    i hope that the PWM output keep Low after the PWM output is done.

    Stop counter in PWM_0_INST's Zero or Load interrupt depending on Low or High.

    DL_TimerG_stopCounter(PWM_0_INST);

    Kelly Li2 said:
    Would you please kinldy let me know how to know the correct register name from MSPM0 L-Series Technical Reference Manual? (Question 1)
    Kelly Li2 said:
    for example, if we want to use these two register of TIMG4, What are their correct names? (Question 2)

    These are same question, here is the step to find the correct register from TRM to IDE, CCS as example:

    Example code: timx_timer_mode_pwm_edge_sleep_LP_MSPM0G3507_nortos_ticlang

    1. PWM_0_INST is TIMG0 and TIMG0 is GPTIMER_Regs type.

    typedef struct {
       uint32_t RESERVED0[256];
  __IO uint32_t FSUB_0;                            /* !< (@ 0x00000400) Subsciber Port 0 */
  __IO uint32_t FSUB_1;                            /* !< (@ 0x00000404) Subscriber Port 1 */
       uint32_t RESERVED1[15];
  __IO uint32_t FPUB_0;                            /* !< (@ 0x00000444) Publisher Port 0 */
  __IO uint32_t FPUB_1;                            /* !< (@ 0x00000448) Publisher Port 1 */
       uint32_t RESERVED2[237];
  GPTIMER_GPRCM_Regs  GPRCM;                             /* !< (@ 0x00000800) */
       uint32_t RESERVED3[506];
  __IO uint32_t CLKDIV;                            /* !< (@ 0x00001000) Clock Divider */
       uint32_t RESERVED4;
  __IO uint32_t CLKSEL;                            /* !< (@ 0x00001008) Clock Select for Ultra Low Power peripherals */
       uint32_t RESERVED5[3];
  __IO uint32_t PDBGCTL;                           /* !< (@ 0x00001018) Peripheral Debug Control */
       uint32_t RESERVED6;
  GPTIMER_CPU_INT_Regs  CPU_INT;                           /* !< (@ 0x00001020) */
       uint32_t RESERVED7;
  GPTIMER_GEN_EVENT0_Regs  GEN_EVENT0;                        /* !< (@ 0x00001050) */
       uint32_t RESERVED8;
  GPTIMER_GEN_EVENT1_Regs  GEN_EVENT1;                        /* !< (@ 0x00001080) */
       uint32_t RESERVED9[13];
  __IO uint32_t EVT_MODE;                          /* !< (@ 0x000010E0) Event Mode */
       uint32_t RESERVED10[6];
  __I  uint32_t DESC;                              /* !< (@ 0x000010FC) Module Description */
  GPTIMER_COMMONREGS_Regs  COMMONREGS;                        /* !< (@ 0x00001100) */
       uint32_t RESERVED11[438];
  GPTIMER_COUNTERREGS_Regs  COUNTERREGS;                       /* !< (@ 0x00001800) */
} GPTIMER_Regs;

    2. In struct of GPTIMER_Regs, if you want to find the CCACT_01(TRM), this should be in:

    GPTIMER_COUNTERREGS_Regs  COUNTERREGS;                       /* !< (@ 0x00001800) */

    3. COUNTERREGS is GPTIMER_COUNTERREGS_Regs type and is define as:

    typedef struct {
  __IO uint32_t CTR;                               /* !< (@ 0x00001800) Counter Register */
  __IO uint32_t CTRCTL;                            /* !< (@ 0x00001804) Counter Control Register */
  __IO uint32_t LOAD;                              /* !< (@ 0x00001808) Load Register */
       uint32_t RESERVED0;
  __IO uint32_t CC_01[2];                          /* !< (@ 0x00001810) Capture or Compare Register 0/1 */
  __IO uint32_t CC_23[2];                          /* !< (@ 0x00001818) Capture or Compare Register 2/3 */
  __IO uint32_t CC_45[2];                          /* !< (@ 0x00001820) The CC_45 register are a registers which can be
                                                      used as compare to the current CTR to create an events CC4U, CC4D,
                                                      CC5U and CC5D. */
       uint32_t RESERVED1[2];
  __IO uint32_t CCCTL_01[2];                       /* !< (@ 0x00001830) Capture or Compare Control Registers 0/1 */
  __IO uint32_t CCCTL_23[2];                       /* !< (@ 0x00001838) Capture or Compare Control Registers 2/3 */
  __IO uint32_t CCCTL_45[2];                       /* !< (@ 0x00001840) Capture or Compare Control Registers 4/5 */
       uint32_t RESERVED2[2];
  __IO uint32_t OCTL_01[2];                        /* !< (@ 0x00001850) CCP Output Control Registers 0/1 */
  __IO uint32_t OCTL_23[2];                        /* !< (@ 0x00001858) CCP Output Control Registers 2/3 */
       uint32_t RESERVED3[4];
  __IO uint32_t CCACT_01[2];                       /* !< (@ 0x00001870) Capture or Compare Action Registers 0/1 */
  __IO uint32_t CCACT_23[2];                       /* !< (@ 0x00001878) Capture or Compare Action Registers 2/3 */
  __IO uint32_t IFCTL_01[2];                       /* !< (@ 0x00001880) Input Filter Control Register 0/1 */
  __IO uint32_t IFCTL_23[2];                       /* !< (@ 0x00001888) Input Filter Control Register 2/3 */
       uint32_t RESERVED4[4];
  __IO uint32_t PL;                                /* !< (@ 0x000018A0) Phase Load Register */
  __IO uint32_t DBCTL;                             /* !< (@ 0x000018A4) Dead Band insertion control register */
       uint32_t RESERVED5[2];
  __IO uint32_t TSEL;                              /* !< (@ 0x000018B0) Trigger Select Register */
  __I  uint32_t RC;                                /* !< (@ 0x000018B4) Repeat counter Register */
  __IO uint32_t RCLD;                              /* !< (@ 0x000018B8) Repeat counter load Register */
  __I  uint32_t QDIR;                              /* !< (@ 0x000018BC) QEI Count Direction Register */
       uint32_t RESERVED6[4];
  __IO uint32_t FCTL;                              /* !< (@ 0x000018D0) Fault Control Register */
  __IO uint32_t FIFCTL;                            /* !< (@ 0x000018D4) Fault input Filter control register */
} GPTIMER_COUNTERREGS_Regs;

    4. You can find CCACT_01 in struct of GPTIMER_COUNTERREGS_Regs.

    --------

    An easier way to find registers: enter debug mode and using Register window, it can show the hierarchy in more detail on the software:

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Prodigy 210 points

    Hi ,

    Thanks very much for your support.

    i have tried to use 'TIMG4_CCACT_01', it seems it didn't work.

    many thanks.

    BR

    Kelly

  • 0 in reply to Kelly Li2
    Guru 100235 points

    I don't have all my materials here, but I'm pretty sure it would look something like:

    > TIMG4->COUNTERREGS.CCACT_01[0] |= GPTIMER_CCACT_01_SWFRCACT_CCP_LOW; /// Force CC0 low

    If looks like you can also do this with Driverlib using something like:

    > DL_Timer_overrideCCPOut(TIMG4, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_DISABLED, 0); // Force CC0 low (but not CC0N)

  • 0 in reply to Bruce McKenney
    Prodigy 210 points

    Hi Bruce,

     thanks very very much.

    it works.

    BR

    Kelly