Multiplexed DMMDATA[15:2] and MIBSPI5 Pin Interoperability

Hi Tony,

DMM_DAT[15:2} and MibSPI5 signals are pinmuxed. Please refer to chapter 4 in TRM (SPNU499) about how to use I/O multiplexing. Table 4-15 shows which registers are used for DMM.  http://www.ti.com/lit/ug/spnu499/spnu499.pdf

1. unlock IOMM registers (unlcok the CPU access to pinmux registers by writing specified value (chapter 4) to kick0 a dn kick1 registers)

int *) 0xFFFFEA38 = 0x83E70B13;  /* kicker 0 register, unlock CPU write access to PINMMR registers */

int *) 0xFFFFEA3C = 0x95A4F1E0;  /* kicker 1 register, */

2. set the pinmux registers to DMM

*(

int *) 0xFFFFEB40 = 0x02010101; //P12 //DMM_DATA[7]

int *) 0xFFFFEB44 = 0x01020202; //P13 //DMM_DATA[4],DMM_DATA[8],DMM_DATA[12]

int *) 0xFFFFEB78 = 0x02020101; //P26 //DMM_DATA[2],DMM_DATA[3]

int *) 0xFFFFEB7C = 0x02020202; //P27 //DMM_DATA[10],DMM_DATA[9],DMM_DATA[6],DMM_DATA[5]

int *) 0xFFFFEB80 = 0x02020202; //P28 //DMM_DATA[15],DMM_DATA[14],DMM_DATA[13],DMM_DATA[11]

3. lock IOMM registers

int *) 0xFFFFEA38 = 0x00000000;  /* kicker 0 register, lock CPU write access to PINMMR registers */

int *) 0xFFFFEA3C = 0x00000000;  /* kicker 1 register, */

4. Configure your DMM function, for exmaple GIO as you did

Regards,

QJ

Tony Morrell said:

Hi,

I am using the multiplexed DMMDATA[15:2] and MIBSPI5 pins for general purpose output. These pins are configured as GPIO outputs in both DMM and MIBSPI5 registers.

My problem is that a write of output data to DMMPC4 (set high) or DMMPC5 (set low) appears to have no effect at the output pin.

 

In the TRM, I can find no mention of DMM within the MIBSPI section, nor MIBSPI within the DMM section.

Configuration registers I set are:

DMMPC0 = 0x00000000 // GIO mode
DMMPC1 = 0x0007FFFF // Output
DMMPC6 = 0x00000000 // Push/pull
DMMPC7 = 0x00000000 // Pull control enabled
DMMPC8 = 0x00000000 // Pull down 

SPIPC0 = 0x00000000 // GIO mode
SPIPC1 = 0x00000FFF // Output
SPIPC6 = 0x00000000 // Push/pull
SPIPC7 = 0x00000000 // Pull control enabled
SPIPC8 = 0x00000000 //  Pull down

My questions are:

 

1. I don't understand the term 'multiplexed' when used with respect to these pins; is there a subtle difference to them being 'shared' or 'multi=purpose'?
2. Do I need to set a multiplex selector register somewhere to route the output from either DMM or MIBSPI5 control registers or should either module's registers control the multiplexed outputs?

Regards, Tony.

Hi Tony,

DMM_DAT[15:2} and MibSPI5 signals are pinmuxed. Please refer to chapter 4 in TRM (SPNU499) about how to use I/O multiplexing. Table 4-15 shows which registers are used for DMM.  http://www.ti.com/lit/ug/spnu499/spnu499.pdf

1. unlock IOMM registers (unlcok the CPU access to pinmux registers by writing specified value (chapter 4) to kick0 a dn kick1 registers)

int *) 0xFFFFEA38 = 0x83E70B13;  /* kicker 0 register, unlock CPU write access to PINMMR registers */

int *) 0xFFFFEA3C = 0x95A4F1E0;  /* kicker 1 register, */

2. set the pinmux registers to DMM

*(

int *) 0xFFFFEB40 = 0x02010101; //P12 //DMM_DATA[7]

int *) 0xFFFFEB44 = 0x01020202; //P13 //DMM_DATA[4],DMM_DATA[8],DMM_DATA[12]

int *) 0xFFFFEB78 = 0x02020101; //P26 //DMM_DATA[2],DMM_DATA[3]

int *) 0xFFFFEB7C = 0x02020202; //P27 //DMM_DATA[10],DMM_DATA[9],DMM_DATA[6],DMM_DATA[5]

int *) 0xFFFFEB80 = 0x02020202; //P28 //DMM_DATA[15],DMM_DATA[14],DMM_DATA[13],DMM_DATA[11]

3. lock IOMM registers

int *) 0xFFFFEA38 = 0x00000000;  /* kicker 0 register, lock CPU write access to PINMMR registers */

int *) 0xFFFFEA3C = 0x00000000;  /* kicker 1 register, */

4. Configure your DMM function, for exmaple GIO as you did

Regards,

QJ

Tony Morrell said:

Hi,

I am using the multiplexed DMMDATA[15:2] and MIBSPI5 pins for general purpose output. These pins are configured as GPIO outputs in both DMM and MIBSPI5 registers.

My problem is that a write of output data to DMMPC4 (set high) or DMMPC5 (set low) appears to have no effect at the output pin.

 

In the TRM, I can find no mention of DMM within the MIBSPI section, nor MIBSPI within the DMM section.

Configuration registers I set are:

DMMPC0 = 0x00000000 // GIO mode
DMMPC1 = 0x0007FFFF // Output
DMMPC6 = 0x00000000 // Push/pull
DMMPC7 = 0x00000000 // Pull control enabled
DMMPC8 = 0x00000000 // Pull down 

SPIPC0 = 0x00000000 // GIO mode
SPIPC1 = 0x00000FFF // Output
SPIPC6 = 0x00000000 // Push/pull
SPIPC7 = 0x00000000 // Pull control enabled
SPIPC8 = 0x00000000 //  Pull down

My questions are:

 

1. I don't understand the term 'multiplexed' when used with respect to these pins; is there a subtle difference to them being 'shared' or 'multi=purpose'?
2. Do I need to set a multiplex selector register somewhere to route the output from either DMM or MIBSPI5 control registers or should either module's registers control the multiplexed outputs?

Regards, Tony.

Hi QJ,

Thanks for the details. I'm going to try it out right now.

I just need to check, does the TRM SPNU499 for the TMS570LS31x replace TRM SPNU489A that I am using for our TMS570LS10216 and 20216? I'm not sure it does. Now, following your information, I have found a reference to MIBSPIP5/DMM Pin Multiplexing in the TMS570LS20216 datasheet (SPNU141E) in section 4.6.2. This seems more applicable to my processor type.

Regards, Tony.

Thanks QJ,

My fault for not specifying the device variant. I'll give your solution a try on my workbench and verify on undoubted success!

Regards, Tony.

Hi QJ,

I think from reading the datasheet that DMM GIO and MIBSPI5 are mutually exclusive. Is this correct?

Regards, Tony.