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MCU-PLUS-SDK-AM243X: SRAM Clock

Hussein Hafez
Prodigy 60 points
Part Number: MCU-PLUS-SDK-AM243X


Hello,

I am using AM243x Launchpad and I was trying to explore the clock tree for the whole controller and I have reached to a good results but I want to know what is the clock source of (OCSRAM), I did not find any configuration for its clock and also I did not find a fixed clock for the RAM, so could you please tell me how to find (OCSRAM)'s clock.

Thank you,
Hussein Hafez.

  • 0
    TI__Guru 63385 points

    The OCSRAM is being clocked from a divided down version of MAIN_SYSCLK0. Why do you need to know which clock is operating the OCSRAM?  It is not user configurable.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 60 points

    I do not want to configure it, I want to know which PLL and HSDIV is used by OCSRAM and I did not find this information in data-sheet directly so I contacted you, if it takes the clock from MAIN_SYSCLK0 that means it uses PLL0 and HSDIV0, right? and what is the division factor before clocking the OCSRAM

    Regards,
    Hussein Hafez.

  • 0 in reply to Hussein Hafez
    TI__Guru 63385 points

    Yes, MAIN_SYSCLK0 originates from the HSDIV0 output of MAIN_PLL0.

    OCSRAM has two clock inputs, VCLK has a divide-by-2 pre-divider and CCLK has a divide-by-4 pre-divider. I'm not familiar with the internal operation of OCSRAM, so not sure the function associated with the two clock inputs.

    We do not put internal functional details in the datasheet. This type of information is typically provided in the TRM.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 60 points

    I have explored the TRM but its to huge so founding a specific information like this is not easy and I tried to find it but I did nit reach to anything, could you guide to to the section that talks about the OCSRAM clock and I will find it myself?

    Regards,
    Hussein Hafez.

  • 0 in reply to Hussein Hafez
    TI__Guru 63385 points

    I'm still not clear what you need to know. Please explain what you are trying to do, so I know what information is needed.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 60 points

    I want to know the functional clock of SRAM, according to PLL0 and HSDIV0 in my side this clock is MAINSYSCLK0 with 500MHz, you said that the OCSRAM takes the clock from this source and divided it by 2 (VCLK) and 4 (CCLK), I want to know which clock of them is the functional clock? and if there any section talks about VCLK and CCLK please guide me to the section, to be very clear what is the clock of reading and writing data on OCSRAM?

  • 0 in reply to Hussein Hafez
    TI__Guru 63385 points

    I found our internal specification for the OCSRAM and it doesn't provide any significant details. It appears vclk is used to clock the read/write data path and cclk is associated with ecc control signals used to indicate an error.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 60 points

    Can you send me this specifications for OCSRAM?

  • 0 in reply to Hussein Hafez
    TI__Guru 63385 points

    No. It is an internal design document.

    Regards,
    Paul