TMS570LS1224: Looking for Example Code for Long DMA Transfers to single buffer in MibSpi Mode

Thomas Seiler

Part Number: TMS570LS1224

Dear e2e forum,

I have successfully used SPI5 in classic mode with DMA, driving SPI transfers by directly writing to / reading from the DAT1/BUF registers with the DMA controller. I prepare "raw" transfers that write the full 32 bits of the DAT1 register so that I can include the control flags to manipulate CSHOLD and WDEL. This technique has been described in this forum and is really useful for performing several SPI transactions in one big DMA transfer.

Now I needed to add another SCI and discovered that, unfortunately, it shares its DMA request lines with the SPI5 classic ones (DMAREQ[30] and [31] to be exact).

As a workaround, I am trying to enable MIB mode on SPI5 and remap the DMA request lines using RXDMA_MAP / TXDMA_MAP. But so far, my transfer stalls after the first byte is transmitted; I think I have an invalid combination of ONESHOT, ICOUNT and RXDMAENA bits, and it would be very helpful if I could compare my settings against a working example.

I have found a relevant example that seems to be very close to what I need: configuring a single transfer group with just a single mibRAM buffer and then driving long transfers through it using DMA.

MIBSPI with DMA triggered from two tasks - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums.

Unfortunately, the zip files in this thread are no longer available.

Do you know of any similar examples that are public?

Thanks a lot and Best Regards,

Thomas

over 1 year ago

0 jagadish gundavarapu over 1 year ago

TI__Guru 70391 points

Hi Thomas,

Can you please refer below thread?

(+) [FAQ] TMS570LS3137: TMS570LS3137 MibSPI5 Tx and Rx with DMA - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

I hope this would be helpful to resolve your issue.

--
Thanks & regards,
Jagadish.

0 Thomas Seiler over 1 year ago in reply to jagadish gundavarapu

Prodigy 10 points

Dear Jagadish,

Thanks for the link. Unfortunately, I have the same issue with this thread, I cannot download these files either.

I have tried with Chrome, Firefox, and Edge and get the same result: You do not have permission to view this directory or page. I have

Any idea what I can try next?

Thanks & best regards,

Thomas

0 jagadish gundavarapu over 1 year ago in reply to Thomas Seiler

TI__Guru 70391 points

Hi Thomas,

Can you please zip your project and attach it. I will verify it and debug it for to find root cause for the issue at my end.

--
Thanks & regards,
Jagadish.

0 Thomas Seiler over 1 year ago in reply to jagadish gundavarapu

Prodigy 10 points

Dear e2e forum, Dear Jagadish,

I cannot share the code for NDA reasons.

My problem was the confusion over the correct configuration for ONESHOT bits when using the DMA to drive a transfer group consisting of a single cell. With the ONESHOT enabled in the TGCTRL[], only the first byte of the transfer was happening; with the ONESHOT enabled in the DMACTRL[], the transfer would happen, but the last byte would be repeated indefinitely, and sometimes some words were duplicated. Any possible combination of these bits would lead to wrong results. The technical reference manual is unclear on how such a setup would work, and I could not find any example code online or any app note on the matter.

The missing insight was this also required BUFMODE flags in the mibRAM control word to be set to either a skip or suspend mode, so that SPI transfers are only triggered when the DMA engine updates the cell.

As reference (and for other forum users), this is the configuration that has worked for me:

/* configure first transfer group for a size of one cell */
TGCTRL[0] = (0U << 30U)            /* disable one-shot for transfer-group, we will drive this from DMA */
          | (0U << 29U)            /* pcurrent reset disabled */
          | (TRG_ALWAYS << 20U)    /* trigger event: always for software trigger */
          | (TRG_DISABLED << 16U)  /* trigger source: disabled */
          | (0U << 8U);            /* start address is first RAM cell */
        
/* configure all other transfer groups for zero size */
for (i = 1; i < 8U; i++)  
TGCTRL[i] = (0U << 30U)            /* disable one-shot for transfer-group, we will drive this from DMA */
          | (0U << 29U)            /* pcurrent reset disabled */
          | (TRG_ALWAYS << 20U)    /* trigger event: always for software trigger */
          | (TRG_DISABLED << 16U)  /* trigger source: disabled */
          | (1U << 8U);            /* start address is second RAM cell */

TGCTRL[8] = (uint32_t)((uint32_t)1U << 8U);
LTGPEND = (LTGPEND & 0xFFFF00FFU); /* end is first cell */

/* initialize the first RAM cell */
mibRAM.tx[0].control = (3U << 13U)  /* buffer mode "Skip Single-Transfer overwrite-protect" to keep sequencer in sync with DMA */
                     | (0U << 12U)  /* chip select hold */
                     | (0U << 10U)  /* enable WDELAY */
                     | (0U << 11U)  /* lock transmission */
                     | (0U << 8U)   /* data format */
                     | (0xFE);      /* chip select CS_0 */
                     
/* disable the other cells */
for (i = 1U; i < 128U; i++) mibRAM->tx[i].control = 0U; /* cell disabled */

/* setup the DMA for Transfer Group 0 */
DMACTRL[0] = (1U < 31U)                 /* enable one-shot mode for DMA */
           | (receive_reqline << 20U)   /* rx internal request line */
           | (transmit_reqline << 16U); /* tx internal request line */

/* switch to DMA large_count mode */
DMACNTLEN = 0x1U;

/* start transfer group */
TGCTRL[0] |= (1U << 31U);

And to start a transfer:

/* setup frame count */
DMACOUNT[0]  = ((transfer_length - 1U) << 16U);                     

/* enable TX & RX DMA bits, this starts the transfer */
DMACTRL[0]  |= (uint32_t)0x0000C000;

As far as I understand, the BUFMODE=3h is required here to keep the DMA and Mib Sequencer in sync.

Thanks and best regards,

Thomas