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AM2631: GPCM/CLKOUT frequencies dependent of the Core/Peripheral/SYS_CLK settings

Javier Rico
Prodigy 70 points
Part Number: AM2631

Hello,

For my project it is necessary to achieve the following frequencies to interface with peripherals:

GPCM: 21.33 MHZ (64 MHz/3)

CLKOUT0: 64 MHz

CLKOUT1: 21.33 MHZ (64 MHz/3)

(besides, periodic interrupts of 2ms and 22ms are also required)

Is it necessary to modify the Core/Peripheral/SYS_CLK frequencies, or can they be achieved just by modifying the peripherals' frequency dividers? The suggested external clock of 25MHz is populated and the root clocks (as in Table 6-25 Root clocks table) used for the time being.

Regards,

Javier

  • 0
    TI__Mastermind 22953 points

    Hey Javier,

    I am looking into your query now. In an ideal situation, only the RCM peripheral clock dividers would be needed to achieve your required operating frequencies, but I will need to double check on achieving these specific values for GPMC and CLKOUT0/1. The RTI module should suffice for providing the 2ms and 22ms periodic interrupts using the default 25MHz XTALCLK source. Please allow a day to provide additional clock tree details for the remaining interfaces.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 70 points

    Thanks Zachary, the clock tree is not clear to me in the reference manual. I just saw that the divider for CLKOUT, CLKOUTn_DIV_VAL, only accepts 16 values (to divide by 1, 2,... to 16), so having an input frequency of 64 Mhz would be ideal, and then share that input frequency for CLKOUT0, CLKOUT1 and GPCM.

  • +1 in reply to Javier Rico
    TI__Mastermind 22953 points

    Hey Javier,

    I did some analysis on this, and I think there is a viable solution utilizing the DPLL_PER_HSDIV0_CLKOUT1 (192 MHz) as the clock source.

     

    CLKOUT0 Config

    CLKOUT0_GCM_CLKSRC_SEL = 4 : DPLL_PER_HSDIV0_CLKOUT1 (192 MHz)

    CLKOUT0_CLK_GCM_CLKDIV = 3 : 192/3 = 64 MHz

     

    CLKOUT1 Config

    CLKOUT0_GCM_CLKSRC_SEL = 4 : DPLL_PER_HSDIV0_CLKOUT1 (192 MHz)

    CLKOUT1_CLK_GCM_CLKDIV = 9 : 192/9 = 21.33 MHz

     

    GPMC Config

    GPMC_CLK_GCM_CLKSRC_SEL = 3 : DPLL_PER_HSDIV0_CLKOUT1 (192 MHz)

    GPMC_CLK_GCM_CLKDIV = 9 : 192/9 = 21.33 MHz

    Please let us know if this meets your requirements and what results return from experimenting with the above configurations.

     

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 70 points

    Thanks, Zachary