Regarding the API for the SD in SDK 9.1.0.6
Please look at the following function (Question below):
/* Initialize SDFM instance */
sdfm_handle SDFM_init(uint8_t pru_id, uint8_t coreId)
{
SDFM *p_sdfm;
if (pru_id == PRU_ID_0)
{
/* Initialize PRU 0 SD */
p_sdfm = &g_sdfm[pru_id];
/* Initialize SDFM control address */
if(coreId == PRUICSS_RTU_PRU0)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + RTUx_DMEM_BASE_ADD);
}
else if (coreId == PRUICSS_PRU0)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + PRUx_DMEM_BASE_ADD);
}
else if (coreId == PRUICSS_TX_PRU0)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + TXPRUx_DMEM_BASE_ADD);
}
else
{
return NULL;
}
/* Set FW PRU ID */
p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
}
else if (pru_id == PRU_ID_1)
{
/* Initialize PRU 1 SD */
p_sdfm = &g_sdfm[pru_id];
/* Initialize SDFM control address */
if(coreId == PRUICSS_RTU_PRU1)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + RTUx_DMEM_BASE_ADD);
}
else if (coreId == PRUICSS_PRU1)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + PRUx_DMEM_BASE_ADD);
}
else if (coreId == PRUICSS_TX_PRU1)
{
p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + TXPRUx_DMEM_BASE_ADD);
}
else
{
return NULL;
}
/* Set FW PRU ID */
p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
}
else
{
return NULL;
}
return (sdfm_handle)p_sdfm;
}
#define PRU_ICSSG_DRAM0_SLV_RAM ( CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE )
#define PRU_ICSSG_DRAM1_SLV_RAM ( CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE )
#define CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE (0x30000000UL)
#define CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE (0x30002000UL)
##define CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE (0x30080000UL)
#define CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE (0x30082000UL)
So my question is, it seems like this API does not take into consideration the ICSSG (PRU number), only the slice ID.
Which means the argument ‘pru_id’ is actually treated as ‘slice_id’.
To make it simpler, I would expect the address assignment to be as following:
|
PRU ID |
Slice ID + Core ID |
Address |
|
0 |
0 = (PRU0) |
CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + PRUx_DMEM_BASE_ADD |
|
0 |
1 = (PRU1) |
CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE + PRUx_DMEM_BASE_ADD |
|
0 |
2 = (RTU0) |
CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + RTUx_DMEM_BASE_ADD |
|
0 |
3 = (RTU1) |
CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE + RTUx_DMEM_BASE_ADD |
|
0 |
4 = (TX0) |
CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + TXPRUx_DMEM_BASE_ADD |
|
0 |
5 = (TX1) |
CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE + TXPRUx_DMEM_BASE_ADD |
|
1 |
0 = (PRU0) |
CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + PRUx_DMEM_BASE_ADD |
|
1 |
1 = (PRU1) |
CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE + PRUx_DMEM_BASE_ADD |
|
1 |
2 = (RTU0) |
CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + RTUx_DMEM_BASE_ADD |
|
1 |
3 = (RTU1) |
CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE + RTUx_DMEM_BASE_ADD |
|
1 |
4 = (TX0) |
CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + TXPRUx_DMEM_BASE_ADD |
|
1 |
5 = (TX1) |
CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE + TXPRUx_DMEM_BASE_ADD |
Please advise.
