• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 331 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP432E401Y: Address Latch Enable for EPI

Mp
Intellectual 350 points
Part Number: MSP432E401Y

I'm currently designing a microcontroller board with MSP432E401Y which uses EPI Host bus muxed mode for interfacing with 3 devices(SRAM, Parallel Flash and FPGA)

To segregate the address and data line, should i add a D-latch for EPI( Referred https://www.ti.com/tool/TIDM-TM4CFLASHSRAM)

Or the internal ALE pin will capture the address and send accordingly?

Is it fine if i directly connect the EPI pins to the devices as A0-EPI0 and D0-EPI0 ?

Please let me know if there is anything that i have to add in my hardware design

 

  • 0
    TI__Guru**** 190986 points

    HI,

      Please refer to the datasheet for details. Yes, you can use the ALE for the D-latch to hold the address until the data phase.

    11.4.3.1 Control Pins
    The main three strobes are Address Latch Enable (ALE), Write (WRn), and Read (RDn, sometimes
    called OEn). Note that the timings are designed for older logic and so are hold-time versus setup-time
    specific. The polarity of the read and write strobes can be active High or active Low by clearing or
    setting the RDHIGH and WRHIGH bits in the EPI Host-Bus n Configuration (EPIHBnCFGn) register.
    The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFGn
    register. The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are
    shared. All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates
    to an external latch to capture the address then hold it until the data phase.

  • 0 in reply to Charles Tsai
    Intellectual 350 points
    Charles Tsai said:
    The ALE indicates
    to an external latch to capture the address then hold it until the data phase.

    okay so i will add the EPI as mentioned below.. will that be the same for FPGA as well or i can connect EPI pins directly without D-Latch?

  • 0 in reply to Mp
    TI__Guru**** 190986 points

    I suppose so since ALE is used if you are using the ADDR/DATA MUX mode. The address and data will come out at different phases, not at the same time.