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AM2434: why ICSSG1 running Ethercat should be configured to 33333333Hz

guxl24
Prodigy 150 points
Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi TI Teams,

Situation: Run ethercat firmware under ICSSG1 in the r5f-0-0 core of am243, and run FSI firmware under ICSSG0 in the r5f-0-0 core. There is a code segment in ICSSG0 PRU as follows: .

 And with these code, the core clock of ICSSG1 running Ethercat can only be configured to 33333333Hz to run Ethercat normally as the following picture shows.

But if the code 'ldi32 r5, 0xD172BC5A ; Kick 1' in ICSSG0 firmware, as shown in the red box in the figure below, is masked. The core clock of ICSSG1 running Ethercat can be configured to run at other frequencies, such as 200000000Hz, and Ethercat can still run normally.

So why does this sentence in ICSSG0 affect the core clock configuration in ICSSG1?  What role did this sentence 'ldi32 r5, 0xD172BC5A; kick 1 'play?

And I also want to know which clock source is the core clock of ICSSG1 running Ethercat firmware? Where was it configured?

 Thanks.

  • 0
    TI__Expert 7385 points

    Hi,

    Thank you for your query.

    Allow me some time to look into this and get back to you.

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    Prodigy 150 points

    I found that the firmware running in PRU-ICSS0 still has the following assembler languages.

    And I also found that PRU-ICSS1’s clock source is also PLL0_HSDIV9 by reading the physical address (0x4300 8044h) as the following picture shows.

    Under this situation, the PRU-ICSS1‘s clock soure is as same as the PRU-ICSS0‘s. So the PRU-ICSS1‘s clock frequency must be as same as the PRU-ICSS0‘s, that is to say 333Mhz . So does this mean that the frequency of the core clock of PRU-ICSS1 set in the following sysconfig is no longer effective?

  • 0 in reply to guxl24
    TI__Mastermind 27290 points

    Hi guxl24,

    Sorry for delay in response.

    guxl24 said:
    FSI firmware

    This is not supported. Still, you can refer  (C:\ti\motor_control_sdk_am243x_09_01_00_06\examples\tidep_01032_dual_motor_drive\single_chip_servo.c\am243x-lp\r5fss1-0_freertos) file and make changes as per your need.

    "tidep_01032_dual_motor_drive reference design.

    There ICSSG0 core clock should be configured to 300 MHz and ICSSG1 core clock should be configured to 200 MHz"

    Best Regards

    Ashwani