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MCU-PLUS-SDK-AM243X: UART with DMA, non-blocking, no interrupt

Part Number: MCU-PLUS-SDK-AM243X

Hi,

we want to use multiple UARTs with DMA, but in non-blocking mode AND without any interrupt.

Our actual concept (non TI) is to trigger TX and RX every x us. Prior this tigger of a new communication we check if RX did finished, if not, we reset the RX DMA prior trigger.

How is this possible with AM243X? The SDK itself does not support that.

I've changed some drivers, but still facing some issues. (How to check if transfer is done or ongoing, etc)

During RX it is possible that a subsystem does response either with 4bytes, or 4bytes + defined number of bytes.

But the ring accelerator + packet dma, does only push the data packet to RAM if the complete number of bytes is transferred.

Any ideas?

best regards
Bastian

  • Hello Bastian,

    I am looking at your queries and you may expect delayed reply as I am in busy other issues fixing .

    Regards,

    S.Anil.

  • Hello Swargam,
    any news at this topic?


    Regards,
    Bastian

  • Hello Bastian,

    Our actual concept (non TI) is to trigger TX and RX every x us.

    The proper method is that DMA should be initiated automatically when a timer event is generated.

    I never tried this method with the UART + PKTDMA and I have used this method for BCDMA memory copy operations.

    I am proposing the same method here.

    If you want to transfer data at a particular X sec or receive data at X sec, this should be through Timer + UART + UDMA driver.

    You have to follow the below steps

    Step 1 : 

    Create Timer interrupt for your X use 

    Step2 : 

    In the above routine, you can call TX UART+UDMA API to initiate the DMA 

    Step3 : 

    Once it's finished, the above steps trigger new data. 

    In UART+, UDMA the driver will use the Udma_ringQueueRaw function which initiates the DMA transfer. If you don't call this function, then DMA will not initiate the DMA transfer. In most cases, we never changed the TX count size. In that case, you can configure all parameters initiation for one time next just call the Udma_ringQueueRaw API to initiate the DMA.

    During RX it is possible that a subsystem does response either with 4bytes, or 4bytes + defined number of bytes.

    Can you please check with the API below 

    Udma_getPeerData by using this API, getting received bytes and not full data bytes, which is implemented in the MCSPI driver and, the try to do the same in the UART driver.

    Typically in UDMA if the total no of bytes received then only user should able see the data .

    Regards,

    S.Anil.

  • Hello Swargam,

    Time triggering the transmit itself is not a problem, but have it with a minimum jitter.

    For the receive problem,
    Udma_getPeerData only delivers the number of received bytes. In principle I want to see the received data, even if the total number of bytes is not reached.

    In addition, I'm struggling with resetting the RX DMA part for the next transfer if the prior one was not complete due to missing bytes. Calling a blocking channel disable is a no go, since we have a real time environment and the transfers need to happen every 125us.

    I'm calling Udma_ringDequeueRaw prior next Udma_ringQueueRaw (to be able to push a new descriptor on queue).

    But if then the count of new arriving data matches total count, the UDMA provides me the incomplete old prior message frame plus some new actual bytes (to fill up the total byte count).

    Regards,
    Bastian

  • Hello Bastian,

    Udma_getPeerData only delivers the number of received bytes. In principle I want to see the received data, even if the total number of bytes is not reached.

    Actually, with UART+PKTDMA, once triggered the DMA , user will see the content after completion of DMA. User can't see the content with out completion of DMA. 

    In addition, I'm struggling with resetting the RX DMA part for the next transfer if the prior one was not complete due to missing bytes. Calling a blocking channel disable is a no go, since we have a real time environment and the transfers need to happen every 125us.

    I'm calling Udma_ringDequeueRaw prior next Udma_ringQueueRaw (to be able to push a new descriptor on queue).

    But if then the count of new arriving data matches total count, the UDMA provides me the incomplete old prior message frame plus some new actual bytes (to fill up the total byte count).

    I am trying to understand how you are running 125usec timeout for RXDMA channel .  Yes, the above behavior is possible once DMA is started. It will read bytes from UART FIFO and put them in the destination memory.

    So, don't have an idea PDMA how much data is moved to destination buffer when data is not available on UART port .

    You can do below steps call Udma_ringFlushRaw next call the Udma_ringQueueRaw function.

    Please share test results. I assume that the above method should work .

    Regards,

    S.Anil.

  • Hello Swargam,

    I do not have a 125us timeout. Our system sends/receives data to/from a subsystem every 125us.

    But it may happen due to disturbance that some bytes are missing during reception (or during change of telegram scheme).

    For example. The RX DMA is configured to receive 8 bytes.

    But until next 125us cyclic interrupt the UART did only received 7bytes - values:{1,2,3,4,5,6,7}. Destination memory is not updated with this data, since PDMA don't want to share the received data.

    Now we want to reset and restart the DMA, for the next transfer.
    This time, 8bytes are received via UART - values:{9,10,11,12,13,14,15,16}. The destination memory is updated this time because 8 bytes are received.
    But the destination memory is updated with the values {1,2,3,4,5,6,7,9}. 7 old bytes, and the first new one.

    Udma_ringFlushRaw did not help either.

    Regards,
    Bastian

  • Hello Bastian,

    I assume that the above proposal should work, but unfortunately, it is not working.

    Let me go through the driver one more time and I will provide suggestions.

    Regards,

    S.ANil.