AM2434: Use DP83826 run gptp_icssg_app_am243x-lp demo failed

example.sysconfig as follow：

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@09.01.00"
 * @versions {"tool":"1.18.0+3266"}
 */

/**
 * Import the modules used in this configuration.
 */
const eeprom     = scripting.addModule("/board/eeprom/eeprom", {}, false);
const eeprom1    = eeprom.addInstance();
const i2c        = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1       = i2c.addInstance();
const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1   = pruicss.addInstance();
const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const enet_icss  = scripting.addModule("/networking/enet_icss/enet_icss", {}, false);
const enet_icss1 = enet_icss.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
eeprom1.$name = "CONFIG_EEPROM0";

i2c1.$name               = "CONFIG_I2C0";
eeprom1.peripheralDriver = i2c1;
i2c1.I2C.$assign         = "I2C0";

debug_log.enableUartLog        = true;
debug_log.enableCssLog         = false;
debug_log.uartLog.$name        = "CONFIG_UART0";
debug_log.uartLog.UART.$assign = "USART0";

const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
const uart_v0_template1 = uart_v0_template.addInstance({}, false);
uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
debug_log.uartLog.child = uart_v0_template1;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 23;

mpu_armv75.$name             = "CONFIG_MPU_REGION5";
mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv75.baseAddr          = 0xA5000000;
mpu_armv75.size              = 23;
mpu_armv75.attributes        = "NonCached";

mpu_armv76.$name    = "CONFIG_MPU_REGION6";
mpu_armv76.size     = 27;
mpu_armv76.baseAddr = 0x60000000;

enet_icss1.$name                                 = "CONFIG_ENET_ICSS0";
enet_icss1.mdioMode                              = "MDIO_MODE_MANUAL";
enet_icss1.QoS                                   = 3;
enet_icss1.timesyncEnable                        = true;
enet_icss1.timesyncSyncOut_pwidth_WC             = 625000;
enet_icss1.addMacAddrCnt                         = 1;
enet_icss1.PktInfoOnlyCount                      = 8;
enet_icss1.GigabitSupportEnable                  = false;
enet_icss1.LargePoolPktCount                     = 56;
enet_icss1.customBoardEnable                     = true;
enet_icss1.useAddMacAddr                         = true;
enet_icss1.txDmaChannel.create(2);
enet_icss1.txDmaChannel[0].$name                 = "ENET_DMA_TX_CH0";
enet_icss1.txDmaChannel[0].PacketsCount          = 8;
enet_icss1.txDmaChannel[1].$name                 = "ENET_DMA_TX_CH_PTP";
enet_icss1.txDmaChannel[1].PacketsCount          = 8;
enet_icss1.rxDmaChannel.create(4);
enet_icss1.rxDmaChannel[0].$name                 = "ENET_DMA_RX_CH0";
enet_icss1.rxDmaChannel[0].PacketsCount          = 8;
enet_icss1.rxDmaChannel[1].$name                 = "ENET_DMA_RX_CH0_PTP";
enet_icss1.rxDmaChannel[1].macAddrCount          = 0;
enet_icss1.rxDmaChannel[1].PacketsCount          = 8;
enet_icss1.rxDmaChannel[2].$name                 = "ENET_DMA_RX_CH1";
enet_icss1.rxDmaChannel[2].chIdx                 = 1;
enet_icss1.rxDmaChannel[2].PacketsCount          = 8;
enet_icss1.rxDmaChannel[2].macAddrCount          = 0;
enet_icss1.rxDmaChannel[3].$name                 = "ENET_DMA_RX_CH1_PTP";
enet_icss1.rxDmaChannel[3].chIdx                 = 1;
enet_icss1.rxDmaChannel[3].macAddrCount          = 0;
enet_icss1.rxDmaChannel[3].PacketsCount          = 8;
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD2.$assign = "PRG1_PRU0_GPO2";

pruicss1.$name                           = "CONFIG_PRU_ICSS1";
enet_icss1.icss                          = pruicss1;
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
pruicss1.intcMapping.create(1);
pruicss1.intcMapping[0].$name            = "CONFIG_ICSS1_INTC_MAPPING0";
pruicss1.intcMapping[0].event            = "41";
pruicss1.intcMapping[0].channel          = "7";
pruicss1.intcMapping[0].host             = "8";

const udma         = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1        = udma.addInstance({}, false);
enet_icss1.udmaDrv = udma1;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
i2c1.I2C.SCL.$suggestSolution                               = "I2C0_SCL";
i2c1.I2C.SDA.$suggestSolution                               = "I2C0_SDA";
debug_log.uartLog.UART.RXD.$suggestSolution                 = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution                 = "UART0_TXD";
enet_icss1.PRU_ICSSG1_MDIO.$suggestSolution                 = "PRU_ICSSG1_MDIO0";
enet_icss1.PRU_ICSSG1_MDIO.MDC.$suggestSolution             = "PRG1_MDIO0_MDC";
enet_icss1.PRU_ICSSG1_MDIO.MDIO.$suggestSolution            = "PRG1_MDIO0_MDIO";
enet_icss1.PRU_ICSSG1_IEP.$suggestSolution                  = "PRU_ICSSG1_IEP0";
enet_icss1.PRU_ICSSG1_IEP.EDC_LATCH_IN0.$suggestSolution    = "PRG1_PRU0_GPO18";
enet_icss1.PRU_ICSSG1_IEP.EDC_SYNC_OUT0.$suggestSolution    = "PRG1_PRU0_GPO19";
enet_icss1.PRU_ICSSG1_MII_G_RT.$suggestSolution             = "PRU_ICSSG1_MII_G_RT";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_COL.$suggestSolution    = "PRG1_PRU0_GPO9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_CRS.$suggestSolution    = "PRG1_PRU0_GPO10";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD0.$suggestSolution   = "PRG1_PRU0_GPO0";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD1.$suggestSolution   = "PRG1_PRU0_GPO1";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD3.$suggestSolution   = "PRG1_PRU0_GPO3";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXDV.$suggestSolution   = "PRG1_PRU0_GPO4";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXER.$suggestSolution   = "PRG1_PRU0_GPO5";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXLINK.$suggestSolution = "PRG1_PRU0_GPO8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD0.$suggestSolution   = "PRG1_PRU0_GPO11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD1.$suggestSolution   = "PRG1_PRU0_GPO12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD2.$suggestSolution   = "PRG1_PRU0_GPO13";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD3.$suggestSolution   = "PRG1_PRU0_GPO14";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXEN.$suggestSolution   = "PRG1_PRU0_GPO15";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_COL.$suggestSolution    = "PRG1_PRU1_GPO9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_CRS.$suggestSolution    = "PRG1_PRU1_GPO10";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD0.$suggestSolution   = "PRG1_PRU1_GPO0";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD1.$suggestSolution   = "PRG1_PRU1_GPO1";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD2.$suggestSolution   = "PRG1_PRU1_GPO2";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD3.$suggestSolution   = "PRG1_PRU1_GPO3";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXDV.$suggestSolution   = "PRG1_PRU1_GPO4";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXER.$suggestSolution   = "PRG1_PRU1_GPO5";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXLINK.$suggestSolution = "PRG1_PRU1_GPO8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD0.$suggestSolution   = "PRG1_PRU1_GPO11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD1.$suggestSolution   = "PRG1_PRU1_GPO12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD2.$suggestSolution   = "PRG1_PRU1_GPO13";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD3.$suggestSolution   = "PRG1_PRU1_GPO14";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXEN.$suggestSolution   = "PRG1_PRU1_GPO15";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MR0_CLK.$suggestSolution = "PRG1_PRU0_GPO6";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MR1_CLK.$suggestSolution = "PRG1_PRU1_GPO6";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MT0_CLK.$suggestSolution = "PRG1_PRU0_GPO16";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MT1_CLK.$suggestSolution = "PRG1_PRU1_GPO16";

enet_custom_board_config.c as follow:

/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdint.h>
#include <enet.h>
#include <networking/enet/core/include/phy/enetphy.h>
#include <networking/enet/core/include/phy/dp83826.h>
#include <networking/enet/utils/include/enet_apputils.h>
#include <kernel/dpl/SystemP.h>
#include <kernel/dpl/AddrTranslateP.h>
#include <networking/enet/core/src/phy/enetphy_priv.h>
#include <drivers/gpio.h>
#include <board/eeprom.h>
#include "ti_board_open_close.h"
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include <drivers/gpio.h>
#include <kernel/dpl/AddrTranslateP.h>



#if (ENETBOARD_SYSCFG_CUSTOM_BOARD == 1)

#define ENET_BOARD_NUM_MACADDR_MAX (3U)
#define I2C_EEPROM_MAC_DATA_OFFSET (0x3D)
#define I2C_EEPROM_MAC_CTRL_OFFSET (0x3B)
#define ENET_GET_NUM_MAC_ADDR(num) ((num>>3)+1)

#define CONFIG_ENET_ICSSG0_PHY0_ADDR (2U)
#define CONFIG_ENET_ICSSG0_PHY1_ADDR (4U)


/* PHY drivers */
extern EnetPhy_Drv gEnetPhyDrvGeneric;
extern EnetPhy_Drv gEnetPhyDrvDp83826;


/*! \brief All the registered PHY specific drivers. */
static const EnetPhyDrv_Handle gEnetPhyDrvs[] =
{
    &gEnetPhyDrvDp83826,   /* DP83826 */
    &gEnetPhyDrvGeneric,   /* Generic PHY - must be last */
};

const EnetPhy_DrvInfoTbl gEnetPhyDrvTbl =
{
    .numHandles = ENET_ARRAYSIZE(gEnetPhyDrvs),
    .hPhyDrvList = gEnetPhyDrvs,
};


/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort);

static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort,
                                                      const EnetBoard_PortCfg *ethPortCfgs,
                                                      uint32_t numEthPorts);

static void EnetBoard_enableExternalMux();

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */


/*!
 * \brief Common Processor Board (CPB) board's DP83826 PHY configuration.
 */
static const Dp83826_Cfg gEnetCpbBoard_dp83826PhyCfg =
{
//    .txClkShiftEn         = false,
//    .rxClkShiftEn         = true,
//    .txDelayInPs          = 500U,  /* Value in pecosec. Refer to DLL_RX_DELAY_CTRL_SL field in ANA_RGMII_DLL_CTRL register of DP83826 PHY datasheet */
//    .rxDelayInPs          = 500U,  /* Value in pecosec. Refer to DLL_TX_DELAY_CTRL_SL field in ANA_RGMII_DLL_CTRL register of DP83826 PHY datasheet */
//    .txFifoDepth          = 4U,
//    .impedanceInMilliOhms = 35000,  /* 35 ohms */
//    .idleCntThresh        = 4U,     /* Improves short cable performance */
//    .gpio0Mode            = DP83826_GPIO0_LED3,
//    .gpio1Mode            = DP83826_GPIO1_COL, /* Unused */
//    .ledMode              =
//    {
//        DP83826_LED_LINKED,         /* Unused */
//        DP83826_LED_LINKED_100BTX,
//        DP83826_LED_RXTXACT,
//        DP83826_LED_LINKED_1000BT,
//    },
};



/*
 * AM64x board configuration.
 *
 * 1 x RGMII PHY connected to am243x-lp CPSW_3G MAC port.
 */
static const EnetBoard_PortCfg gEnetCpbBoard_am243x_lp_EthPort[] =
{
 {    /* "ENET_ICSSG0_SWITCH" */
        .enetType = ENET_ICSSG_SWITCH,
        .instId   = 0U,
        .macPort  = ENET_MAC_PORT_1,
        .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
        .phyCfg   =
        {
            .phyAddr         = 2,
            .isStrapped      = false,
            .skipExtendedCfg = false,
            .extendedCfg     = &gEnetCpbBoard_dp83826PhyCfg,
            .extendedCfgSize = sizeof(gEnetCpbBoard_dp83826PhyCfg),
        },
        .flags    = 0U,
    },
    {    /* "ENET_ICSSG0_SWITCH" */
        .enetType = ENET_ICSSG_SWITCH,
        .instId   = 0U,
        .macPort  = ENET_MAC_PORT_2,
        .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
        .phyCfg   =
        {
            .phyAddr         = 4,
            .isStrapped      = false,
            .skipExtendedCfg = false,
            .extendedCfg     = &gEnetCpbBoard_dp83826PhyCfg,
            .extendedCfgSize = sizeof(gEnetCpbBoard_dp83826PhyCfg),
        },
        .flags    = 0U,
    },
    {    /* "ENET_ICSSG1_SWITCH" */
            .enetType = ENET_ICSSG_SWITCH,
            .instId   = 1U,
            .macPort  = ENET_MAC_PORT_1,
            .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
            .phyCfg   =
            {
                .phyAddr         = 2,
                .isStrapped      = false,
                .skipExtendedCfg = false,
                .extendedCfg     = &gEnetCpbBoard_dp83826PhyCfg,
                .extendedCfgSize = sizeof(gEnetCpbBoard_dp83826PhyCfg),
            },
            .flags    = 0U,
        },
        {    /* "ENET_ICSSG1_SWITCH" */
            .enetType = ENET_ICSSG_SWITCH,
            .instId   = 1U,
            .macPort  = ENET_MAC_PORT_2,
            .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
            .phyCfg   =
            {
                .phyAddr         = 4,
                .isStrapped      = false,
                .skipExtendedCfg = false,
                .extendedCfg     = &gEnetCpbBoard_dp83826PhyCfg,
                .extendedCfgSize = sizeof(gEnetCpbBoard_dp83826PhyCfg),
            },
            .flags    = 0U,
        }
};

/*
 * am243x-lp virtual board used for MAC loopback setup.
 */
//static const EnetBoard_PortCfg gEnetVirtBoard_am243x_lp_EthPort[] =
//{
// {    /* RGMII MAC loopback */
//         .enetType = ENET_ICSSG_SWITCH,
//         .instId   = 0U,
//         .macPort  = ENET_MAC_PORT_1,
//         .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
//         .phyCfg   =
//         {
//             .phyAddr = ENETPHY_INVALID_PHYADDR,
//         },
//         .flags    = 0U,
//     },
//     {    /* RMII MAC loopback */
//         .enetType = ENET_ICSSG_SWITCH,
//         .instId   = 0U,
//         .macPort  = ENET_MAC_PORT_1,
//         .mii      = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_STANDARD },
//         .phyCfg   =
//         {
//             .phyAddr = ENETPHY_INVALID_PHYADDR,
//         },
//         .flags    = 0U,
//     },
//};


/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

static void EnetBoard_enableExternalMux()
{

    /* For AM243x-LP E3 board:
     *  - GPIO_27 - RGMII1 MUX select PIN:
     *        HIGH to select CPSW
     *        LOW  to select ICSS
     *  - GPIO_26 - RGMII1 PHY RST PIN:
     *        LOW to RESET PHY
     */

    /* Address translate */
//    uint32_t rgmii1PhyRst        = (uint32_t) AddrTranslateP_getLocalAddr(CONFIG_ENET_RGMII_PHY_RST_BASE_ADDR);
//    uint32_t prgCpswRgmii1MuxSel = (uint32_t) AddrTranslateP_getLocalAddr(CONFIG_ENET_RGMII_MUX_SEL_BASE_ADDR);
//
//    /* Setup GPIO for CPSW Mux selection */
//    GPIO_setDirMode(rgmii1PhyRst, CONFIG_ENET_RGMII_PHY_RST_PIN, CONFIG_ENET_RGMII_PHY_RST_DIR);
//    GPIO_setDirMode(prgCpswRgmii1MuxSel, CONFIG_ENET_RGMII_MUX_SEL_PIN, CONFIG_ENET_RGMII_MUX_SEL_DIR);
//    GPIO_pinWriteHigh(rgmii1PhyRst, CONFIG_ENET_RGMII_PHY_RST_PIN);
//    GPIO_pinWriteHigh(prgCpswRgmii1MuxSel, CONFIG_ENET_RGMII_MUX_SEL_PIN);
}

static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort)
{
    const EnetBoard_PortCfg *portCfg = NULL;

    if (ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_CPB_ID))
    {
        portCfg = EnetBoard_findPortCfg(ethPort,
                                        gEnetCpbBoard_am243x_lp_EthPort,
                                        ENETPHY_ARRAYSIZE(gEnetCpbBoard_am243x_lp_EthPort));
    }
//    if ((portCfg == NULL) &&
//        ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_LOOPBACK_ID))
//    {
//        portCfg = EnetBoard_findPortCfg(ethPort,
//                                        gEnetVirtBoard_am243x_lp_EthPort,
//                                        ENETPHY_ARRAYSIZE(gEnetVirtBoard_am243x_lp_EthPort));
//    }
    return portCfg;
}

static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort,
                                                      const EnetBoard_PortCfg *ethPortCfgs,
                                                      uint32_t numEthPorts)
{
    const EnetBoard_PortCfg *ethPortCfg = NULL;
    bool found = false;
    uint32_t i;

    for (i = 0U; i < numEthPorts; i++)
    {
        ethPortCfg = &ethPortCfgs[i];

        if ((ethPortCfg->enetType == ethPort->enetType) &&
            (ethPortCfg->instId == ethPort->instId) &&
            (ethPortCfg->macPort == ethPort->macPort) &&
            (ethPortCfg->mii.layerType == ethPort->mii.layerType) &&
            (ethPortCfg->mii.sublayerType == ethPort->mii.sublayerType))
        {
            found = true;
            break;
        }
    }

    return found ? ethPortCfg : NULL;
}

const EnetBoard_PhyCfg *EnetBoard_getPhyCfg(const EnetBoard_EthPort *ethPort)
{
    const EnetBoard_PortCfg *portCfg;

    portCfg = EnetBoard_getPortCfg(ethPort);

    return (portCfg != NULL) ? &portCfg->phyCfg : NULL;
}

int32_t EnetBoard_setupPorts(EnetBoard_EthPort *ethPorts,
                             uint32_t numEthPorts)
{
    EnetBoard_enableExternalMux();

    /* Nothing else to do */
    return ENET_SOK;
}

void EnetBoard_getMacAddrList(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
                              uint32_t maxMacEntries,
                              uint32_t *pAvailMacEntries)
{
    int32_t status = ENET_SOK;
    uint32_t macAddrCnt;
    uint32_t i;
    uint8_t macAddrBuf[ENET_BOARD_NUM_MACADDR_MAX * ENET_MAC_ADDR_LEN];
    macAddrCnt = EnetUtils_min(ENET_BOARD_NUM_MACADDR_MAX, maxMacEntries);
    uint8_t numMacMax;

    status = EEPROM_read(gEepromHandle[CONFIG_EEPROM0],  I2C_EEPROM_MAC_CTRL_OFFSET, &numMacMax, sizeof(uint8_t));
    EnetAppUtils_assert(status == ENET_SOK);
    EnetAppUtils_assert(ENET_GET_NUM_MAC_ADDR(numMacMax) <= ENET_BOARD_NUM_MACADDR_MAX);
    macAddrCnt = EnetUtils_min(ENET_GET_NUM_MAC_ADDR(numMacMax), maxMacEntries);

    EnetAppUtils_assert(pAvailMacEntries != NULL);

    status = EEPROM_read(gEepromHandle[CONFIG_EEPROM0], I2C_EEPROM_MAC_DATA_OFFSET, macAddrBuf, (macAddrCnt * ENET_MAC_ADDR_LEN));
    EnetAppUtils_assert(status == ENET_SOK);

    /* Save only those required to meet the max number of MAC entries */
    /* TODO Read number of mac addresses from the board eeprom */
    for (i = 0U; i < macAddrCnt; i++)
    {
        memcpy(macAddr[i], &macAddrBuf[i * ENET_MAC_ADDR_LEN], ENET_MAC_ADDR_LEN);
    }

    *pAvailMacEntries = macAddrCnt;

    if (macAddrCnt == 0U)
    {
        EnetAppUtils_print("EnetBoard_getMacAddrList Failed - IDK not present\n");
        EnetAppUtils_assert(false);
    }
}


/*
 * Get ethernet board id
 */
uint32_t EnetBoard_getId(void)
{
    return ENETBOARD_AM64X_AM243X_EVM;
}



#endif /* #if (ENETBOARD_SYSCFG_CUSTOM_BOARD == 1) */

DP83826.C  as follow

/*!
 * \file  dp83826.c
 *
 * \brief This file contains the implementation of the dp83826 PHY.
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdint.h>
#include <include/core/enet_utils.h>
#include <priv/core/enet_trace_priv.h>
#include <include/phy/enetphy.h>
#include <include/phy/dp83826.h>
#include "enetphy_priv.h"
#include "generic_phy.h"
#include "dp83826_priv.h"

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#define DP83826_OUI                           (0x080028U)
#define DP83826_MODEL                         (0x13U)
#define DP83826_REV                           (0x01U)

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

static bool Dp83826_isPhyDevSupported(EnetPhy_Handle hPhy,
                                      const EnetPhy_Version *version);

static bool Dp83826_isMacModeSupported(EnetPhy_Handle hPhy,
                                       EnetPhy_Mii mii);

static int32_t Dp83826_config(EnetPhy_Handle hPhy,
                              const EnetPhy_Cfg *cfg,
                              EnetPhy_Mii mii);

static void Dp83826_enableAutoMdix(EnetPhy_Handle hPhy,
                                   bool enable);

static void Dp83826_printRegs(EnetPhy_Handle hPhy);

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

EnetPhy_Drv gEnetPhyDrvDp83826 =
{
    .name               = "dp83826",
    .isPhyDevSupported  = Dp83826_isPhyDevSupported,
    .isMacModeSupported = Dp83826_isMacModeSupported,
    .config             = Dp83826_config,
    .reset              = GenericPhy_reset,
    .isResetComplete    = GenericPhy_isResetComplete,
    .readExtReg         = GenericPhy_readExtReg,
    .writeExtReg        = GenericPhy_writeExtReg,
    .printRegs          = Dp83826_printRegs,
};

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

void Dp83826_initCfg(Dp83826_Cfg *cfg)
{
    /* No extended config parameters at the moment */
}

static bool Dp83826_isPhyDevSupported(EnetPhy_Handle hPhy,
                                      const EnetPhy_Version *version)
{
    bool supported = false;

    if ((version->oui == DP83826_OUI) &&
        (version->model == DP83826_MODEL) &&
        (version->revision == DP83826_REV))
    {
        supported = true;
    }

    return supported;
}

static bool Dp83826_isMacModeSupported(EnetPhy_Handle hPhy,
                                       EnetPhy_Mii mii)
{
    bool supported;

    switch (mii)
    {
        case ENETPHY_MAC_MII_MII:
            supported = true;
            break;

        /* This driver doesn't support RMII interfaces,
         * but the DP83826 PHY does support it */
        case ENETPHY_MAC_MII_RMII:
        default:
            supported = false;
            break;
    }

    return supported;
}

static int32_t Dp83826_config(EnetPhy_Handle hPhy,
                              const EnetPhy_Cfg *cfg,
                              EnetPhy_Mii mii)
{
    const Dp83826_Cfg *extendedCfg = (const Dp83826_Cfg *)cfg->extendedCfg;
    uint32_t extendedCfgSize = cfg->extendedCfgSize;
    bool enableAutoMdix;
    int32_t status = ENETPHY_SOK;

    if ((extendedCfg == NULL) ||
        (extendedCfgSize != sizeof(*extendedCfg)))
    {
        ENETTRACE_ERR("PHY %u: invalid config params (cfg=%p, size=%u)\n",
                      hPhy->addr, extendedCfg, extendedCfgSize);
        status = ENETPHY_EINVALIDPARAMS;
    }

    /* Auto-MDIX should be disabled in near-end loopback modes */
    enableAutoMdix = !cfg->loopbackEn;

    /* Enable Auto-MDIX and Robust Auto-MDIX */
    if (status == ENETPHY_SOK)
    {
        Dp83826_enableAutoMdix(hPhy, enableAutoMdix);
    }

    return status;
}

static void Dp83826_enableAutoMdix(EnetPhy_Handle hPhy,
                                   bool enable)
{
    ENETTRACE_DBG("PHY %u: %s automatic cross-over %s\n",
                  hPhy->addr, enable ? "enable" : "disable");
    EnetPhy_rmwReg(hPhy, DP83826_PHYCR,
                   PHYCR_AUTOMDIX_ENABLE,
                   enable ? PHYCR_AUTOMDIX_ENABLE : 0);

    if (enable)
    {
        ENETTRACE_DBG("PHY %u: enable Robust Auto-MDIX\n", hPhy->addr);
        EnetPhy_rmwReg(hPhy, DP83826_CR1,
                       CR1_ROBUSTAUTOMDIX,
                       CR1_ROBUSTAUTOMDIX);
    }
    else
    {
        EnetPhy_rmwReg(hPhy, DP83826_PHYCR,
                       PHYCR_FORCEMDIX_MASK,
                       PHYCR_FORCEMDIX_MDI);
    }
}

static void Dp83826_printRegs(EnetPhy_Handle hPhy)
{
    uint32_t phyAddr = hPhy->addr;
    uint16_t val;

    EnetPhy_readReg(hPhy, PHY_BMCR, &val);
    EnetUtils_printf("PHY %u: BMCR    = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_BMSR, &val);
    EnetUtils_printf("PHY %u: BMSR    = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_PHYIDR1, &val);
    EnetUtils_printf("PHY %u: PHYIDR1 = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_PHYIDR2, &val);
    EnetUtils_printf("PHY %u: PHYIDR2 = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_ANAR, &val);
    EnetUtils_printf("PHY %u: ANAR    = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_ANLPAR, &val);
    EnetUtils_printf("PHY %u: ANLPAR  = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_ANER, &val);
    EnetUtils_printf("PHY %u: ANER    = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_ANNPTR, &val);
    EnetUtils_printf("PHY %u: ANNPTR  = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_ANNPRR, &val);
    EnetUtils_printf("PHY %u: ANNPRR  = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, DP83826_CR1, &val);
    EnetUtils_printf("PHY %u: CR1     = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
    EnetUtils_printf("PHY %u: STS1    = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
    EnetUtils_printf("PHY %u: 1KSCR   = 0x%04x\n", phyAddr, val);
    EnetPhy_readReg(hPhy, DP83826_PHYCR, &val);
    EnetUtils_printf("PHY %u: PHYCR   = 0x%04x\n", phyAddr, val);
}

Hi,

Thank you for providing the above files and details.

Allow me some time to look into this. I will get back to you.

Regards,

Nitika