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AM2632: PRU eGPI and eGPO Mapping to Pins at Device Level

Pouya Sabouriazad
Prodigy 120 points
Part Number: AM2632
Other Parts Discussed in Thread: AM3358

Hi,

I have a question about routing the eGPI and eGPO to the device-level pins. According to the Datasheet, the PR0_PRUn_GPIO mode can be configured for a pin at a device level, however I couldn't find  any information about configuring that pin to be an input (connected to eGPI and read from R31) or an output (connected to eGPO and modified through R30). For example, both eGPI0 and eGPO0 from PRU0 are muxed to PR0_PRU0_GPIO0 on Pin K17. What register contains the mux setting? 

Thanks,

Pouya

  • 0
    TI__Mastermind 23043 points

    Hello Pouya,

    When the device pin is mapped to PRm_PRUn_GPIOx at the system-level, and mapped to GPIO (Mode 0) at the PRU-ICSS level, it will operate as either eGPI (when reading from R31) or eGPO (when writing to R30). There are no additional registers to be configured.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 120 points

    Hi Zackary,

    Thank you for your response. I am still confused. It might help to explain what I am trying to do. 

    Devboard Used: LP-AM263X

    PRU is configured to be in GPIO mode and Direct mode is selected for both eGPI and eGPO.

    I have a GPIO that is configured to be an output and it toggles every 500ns. I have connected that GPIO to  pin K16 which is configured as PR0_PRU0_GPIO4. The PRU firmware task is to monitor PR0_PRU0_GPIO4 (R31 bit 4). Upon detection of Rising edge 4-bit counter value is incremented and outputted on PR0_PRU0_GPIO 0-3 by writing to R30 bits 0-3.

    According to my understanding from your explanation, writing to R30 will treat the configured pin as PR0_PRU0_GPIOn at device-level pins as an output. This means that when updating the R30 register with 4-bit counter value, the bit 4 will be written to and causing the PR0_PRU0_GPIO4 to be treated as an output. This will cause damage to the board since two outputs are connected: GPIO and PR0_PRU0_GPIO4. Could you please elaborate on this?

    Also, I have noticed that other Sitara processors like AM3358 have resolved this by providing different configuration mode for PR_PRU_EGPO and EGPI at the device-level pin.

    But this is not a case for AM263X.

    Thanks,

    Pouya

  • 0 in reply to Pouya Sabouriazad
    TI__Mastermind 27824 points

    Hi

    The input or output configuration for a PRU GPIO is controlled using ICSSM_PURx_GPIO_OUT_CTRL register. Please see section "6.1.7.6 ICSSM Global Configuration" in AM263x Technical Reference Manual for more details.

    With this, only pins which are configured for output will be controlled using R30.

    Regards

    Dhaval

  • 0 in reply to Dhaval Khandla
    Prodigy 120 points

    Hi Dhaval,

    There is no section 6.1.7.6 in the latest AM263X TRM (Rev E). I searched for the register name in AM263x Register Addendum (Rev D) document, but couldn't find the register.  

    Thanks,

    Pouya

  • +1 in reply to Pouya Sabouriazad
    TI__Mastermind 27824 points

    Hi

    Sorry, I was referring to an older version of document.

    You can check section 6.1.3.2.5 ICSSM Global Configuration in the latest revision (Rev E). 

    You can check sections 2.3.91 CFG0_PRU-ICSS_PRU0_GPIO_OUT_CTRL Registers and 2.3.92 CFG0_PRU-ICSS_PRU1_GPIO_OUT_CTRL Registers in Register Addendum.

    Regards

    Dhaval