AM2431: Max possible PSRAM memory on GPMC

Hello Praveen,

I am looking at your queries.

You may expect a reply in one or two days.

Regards,

S.Anil.

Hello Praveen,

Praveen Kumar R said:

As per my understanding from the TRM, the GPMC module has 22 address lines so can address upto 4M x 16 bit = 8MB memory. Can you confirm this is correct?

Yes, your understanding is correct . The maximum we can connect to 8MB of memory. 

Praveen Kumar R said:

 Also, is it possible to interface "8M x 16" or "16M x 16"  PSRAM by adding additional address lines from GPIO?

This is not possible since the GPMC peripheral does not have the intelligence to decode address space based on the GPIO signals.

Regards,

S.Anil.

Hi Anil,

Thanks for the input.

We require 16/32 MB of RAM so we want to consider stacked approach (2* 4Mx16 or 4* 4M*16).

One of the part number we are considering to use is:  AS1C8M16PL-70BIN which is 2* 4Mx16. It has Address and Data Lines Multiplexed. 

As per TRM, AM243 supports 32bit or 16 bit A/D Multiplexed memory, however I could not find any related options in the sysconfig tool to configure the GPMC for this setup. Is the SDK support released for this? I'm using the latest SDK (09_01_00_41).

Regards,

Praveen

Hello Praveen,

Sorry for the delayed response, as I am supporting  in other customer escalations.

So, now you want to connect 4M * 16 * 2 or 4M * 16 * 4 with the address, and the data lines are the same for all devices, but the CS address line will be changed.

I assume that this is possible theoretically since in our SOC we have 4 CS lines and each one can handle 4M*16Bytes ranges.

Coming to software support on this connection. Till now, we have not supported PSRAM connection support, and in the MCU+SDK, we do support interfaces with NAND devices, and I think this can be released in the next few releases for single PSRAM support and not for stacked connection support.

On the software side, you need to select 4CS lines for different addresses spaces of CS while writing and reading each memory.

I can confirm with the design engineer whether we can go with a stacked connection or not and let you know.

Regards,

S.Anil.

Hi Anil,

Thanks for your response.

I would like to get some more clarification on the below points:

1) Expected timeline for SDK release which will support Single PSRAM setup.

2) Will this release also include support for both Multiplexed and Non-Multiplexed configuration? 

Regards,

Praveen

Hello Praveen,

Internally, I discussed with the Development  team to get more clarification on dates.

I can say that it will come around 10.1 versions . the rough date is Sept 2024.

In the MCU+SDK we support 16Bit and non-mutiplexed configurations.

Still I need to get the details for the above stack connection reply from the Design Team.

I am reminded them again today, once I get the reply from them, I will update the status.

Regards,

S.ANil.

Hello Praveen,

Swargam Anil said:

I assume that this is possible theoretically since in our SOC we have 4 CS lines and each one can handle 4M*16Bytes ranges.

My assumption is correct.

We need to configure that each chip selection range is 8MB, which is not supported, and the minimum granularity is 16M byte size, needs to be configured.

Now, we are using 4 chip selections and each CS size is 16M bytes and the total is 64M bytes, which will be within the limit of a total of 128M bytes of GPMC data space.

We have not tested this type of stack connection on our EVM. 

While designing these types of stack interfaces for the SOC below are suggestions given by the HW team. 

I assume that you are running a GPMC peripheral at 133MHz.

"133MHz requires very tight timing closure, made worse with slow rise/fall times with 4 capacitive loads.

A simulation may be required to check setup/hold times. We’d want the memories all placed very close to SOC. Branching of signals will cause reflections which need to settle before being considered stable for setup time. You need to run a quick IBIS sim to show these effects "

May I know why you want to interface PSRAM instead of DDR memories ?

Regards,

S.Anil.