AM2434: DP83286 custom drive on AM2434

Hi Andrea

I'm reassigning this to our networking expert. This may need inputs from the PHY team.

Will respond with the details by end of the week.

Regards

Karan

Hi Andrea,

We are working on this.

Hopefully you are referring below documentation for custom PHY integration
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/09_01_00_41/exports/docs/api_guide_am243x/enetphy_guide_top.html

Regards

Ashwani

Hi Ashwani,

thank you for your answer, I'll take a look at this guide and let you know if I find a solution.

Best Regards,

Andrea

Hello Ashwani,

after reading the guide you sent me I noticed that it suggests to add the init of the new phy in the folders <ENET_LLD>/include/phy and <ENET_LLD>/src/phy, although the example project I'm using utilizes the CUST_PHY_base.c and CUST_PHY_xxxxx to initialize the phy.

This is the documentation about the example project https://dev.ti.com/tirex/explore/content/ind_comms_sdk_am243x_09_01_00_03/docs/am243x/ethernetip_adapter/eip_quickstart_example.html.

I added my file CUST_PHY_dp83826, but the phy keeps giving me the same issues.

I'm wondering if this could be related to the extended registers (IEEE 802.3ah clause 22 to access clause 45). I saw them being mentioned in different parts of the program and in the datasheets, but I couldn't find anywhere a register map, maybe I'm not setting something there.

Regards,

Andrea

Hi Ashwani Goel,

is there an update on this topic?

Thanks,

Andrea

Hi

sorry if I insist, but my project is on standby waiting for the phy to work.

Do you have a prediction on when an update will be available? Will it be in a few weeks, couple of months...?

Alternatively, is there a way where I can modify the stack's source code that controls the phy?

Best Regards,

Andrea

Hi Andrea, let me check internally what is the estimated time and come back to you.

thank you,

Paula

Hi Paula,

I already checked the CUST_PHY_dp83869 files in the MCU-SDK and used it as a starting point to create the CUST_PHY_dp83826.c and CUST_PHY_dp83826.h files that I'm using. But I'm still encountering the issue mentioned at the beginning of this thread:

Andrea Favero said:

After comparing the PHY's registers values that I read from my board with the ones contained in Table 3-1 of this guide "DP83826 Troubleshooting Guide", I noticed that register 0x0006 is at 0xF instead of 0x7. This means that DP83826 has detected a fault has during the parallel detection process.

Andrea Favero said:

One other problem I have encountered is inconsistency between the value read using MDIO_phyLinkStatus and CUST_PHY_readReg(0x01); in particular CUST_PHY_readReg shows the correct link status, meanwhile MDIO_phyLinkStatus returns the opposite value.

I'll be waiting for your Custom PHY DP83826.

Thank you,

Andrea

Hi Andrea, I send you my email by private message

thank you,

Paula

Hi Paula,

I tested my board with your example, but I'm still encountering the same behaviour from the PHY in the ethernetip_adapter_discrete_io_device_mii_demo_am243x-lp_r5fss0-0_freertos_ti-arm-clang 

Regards,

Andrea

Hi Andrea, I will re-assign to one of our experts for further support. 

Just to clarify, you are facing same issue as mentioned in your first post?

thank you,

Paula

Hi,

yes the issues I'm facing are the same mentioned in the first post

Thanks for confirming

Paula