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Periodic ADC convertion using hardware trigger whitout cpu usage

sylvestre
Prodigy 80 points

I expect to convert ADC sample contiously at a givien frequency whitout cpu usage. 

  1)  I try It using RTI Comp0 event as hardware trigger but I have to reset the trigger event manually at each conversion. 
        Is it possible to tell the ADC to reset the RTI event when he  acknolegede the event?

 

   Thanks, 
   David

 

 



  

   

 

 

  • 0
    TI__Expert 7650 points

    David,

    We have received your post.  Sorry for the delay responding.  We will get back with your shortly.  

    Brian

  • 0
    TI__Mastermind 49120 points

    Hello David,

    There is no direct mechanism for the ADC to be able to acknowledge the RTI compare event. What is really required is for the interrupt status flag inside the RTI module to be cleared in time, so that it can get set again and continue generating the required periodic triggers to the ADC.

    The RTI compare 0 event is also connected as a DMA request source # 12. You can program a control packet to write to the RTI interrupt flag register to clear the compare 0 status flag. This DMA clear will work in the background and the ADC will have been triggered by then.

    Let me know if you have any questions.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 830 points

    Hello Sunil.

    Regarding

    "The RTI compare 0 event is also connected as a DMA request source # 12. You can program a control packet to write to the RTI interrupt flag register to clear the compare 0 status flag. This DMA clear will work in the background and the ADC will have been triggered by then."

    from the above statement: For the TMS570LS31x this is not possible - reason: The "the RTI interrupt flag register to clear the compare 0 status flag" is RTIINTFLAG, and all of its bit fields could only be cleared in privileged mode (see also spnu499a.pdf, page 457, Figure 13-38), BUT the DMA is only working in user mode (see spnu499a.pdf, page 535, chapter 16.2: "If the DMA writes to registers which are only accessible in privileged mode, the write will not be performed.")

    2 questions:

    1. Can you confirm my statement?

    2. If 1st yes: Can you state another solution?

    Regards,

    Oliver.

  • 0 in reply to oliver.gruendonner
    Intellectual 830 points

    Hello.

    It would be nice to know if you (TI) are analysing my above question, which I raised on 19.11.?

    Thanks and regards

    Oliver.

  • 0 in reply to oliver.gruendonner
    TI__Mastermind 49120 points

    Hello Oliver,

    I have been looking into this, and just did not get an opportunity to reply sooner.

    Your comment about the privileged mode access requirement for clearing the RTI flag is correct. This cannot be done with a DMA access. There is an interrupt flag clearing mechanism built in to the RTI module itself. Unfortunately, this mechanism is not well documented, actually not documented at all. I will try to describe this mechanism and make sure that subsequent updates to the TRM include this information.

    The RTI module has an automatic compare interrupt flag clear mechanism, which is enabled by the RTIINTCLRENABLE register at address offset 0xAC.

    The default values for each of the fields in this register is 0x5 causing the interrupt clear mechanism to be disabled. Writing any other value (preferably 0xA) enables this automatic clear mechanism.

    The registers at address offsets 0xB0, 0xB4, 0xB8 and 0xBC are used to provide the 32-bit compare values for generating the clear conditions for the compare0, compare1, compare2 and compare3 interrupt flags, respectively.

    The "update compare" registers are also used to automatically update these interrupt clear compare values. This allows you to generate a pulse train on the RTI compare interrupts, useful for triggering ADC conversions without having to manually clear the interrupt flag.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 830 points

    Hello Sunil.

    Thank you for your update! I've tried it out, it works. Now the ADC could be triggered by the RTI on a periodic base WITHOUT any SW-intervention.

    I've just one doubt: In spnu499a.pdf (http://www.ti.com/litv/pdf/spnu499a) is stated on page 437 for those registers, which you described above: "Reserved. Do NOT use."

    So now I'm in a dilemma: On the one hand you stated here that this could be used, on the other hand in the official TMS570LS31 Technical Reference Manual is stated to not use these registers. So could you confirm that these registers could really be used without any other concerns?

    Regards, Oliver.

  • 0 in reply to oliver.gruendonner
    TI__Mastermind 49120 points

    Oliver,

    As I stated, this feature will be included in the next updates to the TRM. There are no other concerns with using this feature. The application must ensure that it does not choose to automatically clear the interrupt flag for RTI compare interrupts that it expects to service in an interrupt service routine.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 830 points

    Ok, thank you.

    Regards, Oliver.