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AM263P4: ECAP SOC

Reza Niknezhad
Prodigy 40 points
Part Number: AM263P4

Hi team,

Is there any way to delay the SOC of an ECAP event? basically we want to make sure that our input signal rising period is passed then trigger the ADC to capture the high level, so need a way to delay between the ECAP  event and ADC SOC.

Regards

Reza

  • 0
    TI__Guru*** 135355 points

    Hello Reza,

    So I have this query out to our design team as well, but looking through both the ECAP and the ADC, I think there is a potential that an ADC feature may be able to help with this.

    The ADC has a Trigger Phase Delay feature (Section 7.5.2.4.2.2.3 of TRM) which allows for the delay of sampling by a number of SYSCLK cycles. The number can be up to 65535 cycles so at 400MHz you'd be looking at approx. 163 uS max delay possible. Would that be within the range you are looking for, or do you need a longer interval?

    I will be asking our designers on their thoughts about this feature for your use case as well and will circle back with any comments I get on that.

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    Prodigy 40 points

    Hi Ralph,

    thanks for the reply.
    163uS is enough for our application, but can't find anything about that in the latest SDK, is it still not implemented? aka should I manually define and set those registers?

    Regards

  • 0 in reply to Reza Niknezhad
    TI__Guru*** 135355 points

    Hi Reza,

    I need to follow up with our design team regarding the registers as the details I got from them over the weekend don't match up with my understanding of available registers, particularly when it comes to the trigger selects.

    The general idea is that you'd need to use the ADC repeater block to achieve this and you'd select a TRIGSEL for the ADCSOCxCTL register to be for REPx, and then use the REPxCTL register to select the ECAP trigger. The NSEL setting in the ADC REPxN register would be configured as 0 as we only need 1 trigger.

    Also the SysClk would be 200MHz so the actual max delay would be 327uS.

    Best Regards,

    Ralph Jacobi

  • +1 in reply to Ralph Jacobi
    TI__Guru*** 135355 points

    Hi Reza,

    So the feature we are recommending to use for your situation is the repeater block and that is an IP unique to AM263P compared to AM263. We are still closing on the required documentation updates to the registers for AM263P including the ADC chapter which has multiple new features. Furthermore, some of the register changes were already captured but are not part of the current RA from November. They will be in the next revision targeted for mid-April.

    As for the detail you need, the REP1TRIG and REP2TRIG options for TRIGSEL in the ADCSOCxCTL are at 126/127 (0x7E/0x7F) respectively. These would have to be manually defined by you for now.

    Best Regards,

    Ralph Jacobi