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AM2432: PRU Custom function block pin maping

Part Number: AM2432
Other Parts Discussed in Thread: PROFIBUS

Hi TI experts,

    The AM243X has two PRU subsystem and one of them has 6 RSIC core. If I want program the 6 core for custom function,such as UART.

How to design the AM243X chip physical pin map to the custom function pin.

  • Hi

    The pin mapping for the AM243x is described in Table 6-1. Pin Attributes in the SoC datasheet.

    https://www.ti.com/lit/ds/symlink/am2434.pdf

    Regards

    Karan

  • Hi Karan,  

         As I know one PRU-ICSSG has 2 PRU/2PRU_PRU/2TX_PRU,and the AM243X each PRU-ICSSG has 40 PRGx_PRUx_GPOxx PIN(20 for Core PRU0/20 for Core PRU1).Now I want to use each RSIC for customization UART, totally 6 UART.

         For the hardware design, my question is how to match the PRGx_PRUx_GPOxx pin with the customization UART firmware function?

         Whether the PRGx_PRUx_GPOxx pin can be allocated by software program?

  • Hi

    I'm checking this internally, will get back to you on this thread.

    Regards

    Karan

  • Hello Aiden,

    I support PRU, but not AM243x. I will provide some comments from the PRU side.

    What is in a PRU_ICSSG instance?

    Each PRU_ICSSG instance contains 6 cores (3 cores per "slice"), but each of those cores does NOT necessarily have access to the processor pins. Usually customers will use the PRU core to send and receive signals in and out of the processor pins, and the RTU core (which does NOT have access to the external pins) to move data around, perform calculations, etc. TX_PRU cores can be more flexible depending on the usecase. So you will often have multiple cores all working together on the same software.

    Each PRU_ICSSG instance also contains 1 Hardware UART instance. For more information about which peripherals are in which PRU subsystems, you can refer to app note https://www.ti.com/lit/sprac90

    There are 2 different ways you could theoretically do PRU UART:

    1) Use the hardware UART instance. This behaves like any other UART peripheral on the board, so it could be controlled from the PRU cores, or from an external core like R5F.

    I am not sure whether we have written a driver for AM243x/AM64x to allow an R5F core to control the PRU instance, but I can point to the RTOS and the Linux code where we did it on older devices.

    2) Use the PRU cores to emulate a UART (or multiple UART instances). This is called "soft UART".

    I suspect that we have NOT yet written "soft UART" code for AM243x/AM64x, but you can find more information about the concept in this AM335x documentation: https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/AM335X/linux/Foundational_Components_PRU-ICSS_PRU_ICSSG.html#pru-icss-soft-uart

    With that information, please clarify if you are looking for something specific. 

    Regards,

    Nick

  • Hi Nick,

        Thanks for your support. We want to use the "soft UART" mode, as I know the PRU0/1 is programable. I suppose the R30/31 register is used for allocation the GPIO.

        If I use 6 cores for 6 "soft UART". Whether the AM243X PRU side physical pin mapping to "soft UART" firmware TX/CTS/RTS/RX function pin is flexible?

        Looking forward your reply.

  • Hello Aiden,

    I will provide general information about how soft UART was implemented on previous devices, then my team mates will follow up on what software (if any) is currently provided by TI 

    There is not a one-to-one mapping between 1 PRU core and 1 software UART instance. Since the PRU cores are directly reading and writing to the PRU GPI/PRU GPO signals through the R30/R31 register, the limitation of "max number of software UARTs per PRU core" actually comes down to how many PRU assembly instructions you can execute, and still meet the UART protocol's timing requirements.

    On AM335x (2 PRU cores per PRU-ICSS, where the PRU cores ran at 200MHz), we could support up to 3 software UART instances per PRU core, or 6 software UART instances total.

    The documentation for the AM335x RTOS and Linux PRU software UART implementation is here:
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/890322/beaglebk-soft-uart/3292657#3292657

    The PRU firmware source code for the AM335x PRU software UART implementation is here:
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1039445/processor-sdk-am335x-iso7816-on-pru-of-am335x/3859860#3859860

    As of SDK 9.1, we have not ported the PRU soft UART implementation to AM62x (PRUSS) or AM64x (PRU_ICSSG), at least from the Linux side. 

    Future readers, if you want to followup on the status of PRU Soft UART on AM62x, please reference PROC_SOC-3700 when you ask. I am not aware of an existing requirement to port PRU soft UART to AM64x for either Linux A53 or RTOS R5F.

    Regards,

    Nick

  • Hello Aiden,

      let me clarify the various UART options on the AM243x device first.

    Following UARTs are possible:

    1. Standard UART on the device which has driver in SDK. This is limited to 10 MHz and does not have real-time trigger which is needed for motor application.

    2. ICSS_G hardware UART which was initially brought into ICSS_G IP for low latency 12 Mbit Profibus communication

    3. PRU software UART which uses PRU GPIO to emulate UART. This was typically used on older devices (AM335x) to get additional standard UART.

    4. ICSS_G 3 peripheral interface can be used to implement serial interfaces including UART, known encoder protocols (HDSL, ENDAT, Tamagawa, BISS) or custom serial interface with line code. It supports time triggered start and higher data rates e.g. 25 Mbit.

    As you are asking for 6 UARTs I recommend to use 3 peripheral interface which is available on each slice of one ICSS_G instance. There is also a SDK example with Tamagawa Interface using 3 peripheral interface as UART.

    Pin mapping is described in AM243x TRM  Table 6-422. PRU GPI/GPO Signals and Configurations for Peripheral I/F.

    Note that there is also an alternative pin mapping shown in Table 6-391. PRU_ICSSG<k> I/O Signals and controlled by ICSSG_SA_MX_REG[7] G_MUX_EN register. You cannot mix signals from both settings. 

    Here is a example pin assignment for 6 UARTs on ICSS_G0 using default pin mapping with G_MUX_EN=0.

    - Thomas

  • Hi Thomas,

         Thanks for your reply. This resolved my issue.