AM2632: Delay Between SPI Words

Pouya Sabouriazad

Part Number: AM2632

Hi,

I am using AM2632 MCSPI in FIFO mode to communicate with a ADC. The ADC requires 420 ns delays between SPI words. How can I configure the MCSPI in FIFO mode to insert a delay of 420 ns between de-assertion of chip select line and the next assertion of chip select line?

Thanks,

Pouya

over 2 years ago

0 QJ Wang over 2 years ago

TI__Guru**** 200206 points

Hi Pouya,

TCS0 of MCSPI_CHCONF register will change the delay between CS assertion and first clock edge.

INITDLY insert a delay to the first McSPI word.

0 Pouya Sabouriazad over 2 years ago in reply to QJ Wang

Prodigy 140 points

Hi QJ,

Thank you for your response, I am looking for the CS de-assertion to CS next assertion delay. TMS570 families have wait time setting that corresponds to this delay (WDelay: Delay between transmissions). However, I can not find similar setting to configure this delay in AM2632. I was wondering if there is a way that I can control the duration that the CS is inactive between consecutive SPI transmissions (CS de-assertion to CS next assertion delay). The ADC I am interfacing with requires this delay to be 420ns.

Thanks,

Pouya