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AM2634: SysCfg errors adding ETHPHY drivers

Part Number: AM2634

Hey Sitara MCU team,

I have a customer evaluating the AM2634 for a new project and they are running into SW errors while using the SDK and SysCfg. Please see a summary of the issues and inquiries below and let us know if you need any additional information to provide feedback.

In summary, we are facing the following issues:

  1. In attempting to add ETHPHY drivers to our project via our SysCfg, we are presented with the below reference errors. Both the source/header files where the errors occur and the source/header files in which the references exist are auto generated.

 

E.g.'CONFIG_ETHPHY_NUM_INSTANCES' error occurs in 'ti_board_open_close.h'. That macro exists in 'ti_board_config.h' (also auto generated) and is included in 'ti_board_open_close.h'. Playing with the project Properties>Build>Arm Compiler>Include Options paths results in no improvements.

E.g. CSL_ICSS_M_PR1_xxx does not exist anywhere in any auto generated files and I could not find a reference for it in any TI documentation.

  1. We DO have Enet (CPSW) drivers generating correctly in our project. I am going to spend some time today trying to use the EnetPhy_writeReg and associated functions found in enetphy.c. Is this a better alternative to ETHPHY? If this fails, we will have to resort to bit-banging the MDIO registers manually.

Please advise and thank you for your support.

Best regards,

Matt Calvo

  • Hi Matt,

    Some questions:

    1. Can I please know what Customer's end application use case is. Are they using the on-board PHY (DP83869HMRGZT, DP83826ERHBT) or they are using some other PHY. I wanted to understand why are we adding ETHPHY to the project.

    2. Does the customer want to use CPSW or ICSSM

    3. The error that is shown is related to ICSSM EMAC library. icss_emac library was moved to industrial communications SDK and is not a part of MCU_PLUS_SDK. Incase the customer is interested in ETHPHY and ICSSM, I would recommend looking at the examples in Industrial Communications SDK rather than the MCU_PLUS_SDK.

    Regards,

    Shaunak

  • Thanks for the reply Shaunak!

    I'll pass this along to the customer and will have them comment back on here directly with feedback and answers to your questions!

    -Matt

  • Hi Shaunak,

    Thanks for your reply. Since we asked the question, we have found out that we cannot use ETHPHY as we are using the CPSW.

    We are currently using the following code to attempt to add a PHY link on a DP83TC81x chip:

      uint8_t ConfigDP83TC812(void) {
        uint8_t retVal = 0;
        EnetPhy_Cfg phyCfg;
        EnetPhy_Handle phyHandle;
        EnetPhy_LinkCfg linkCfg;
        bool linkUpStatus = false;
    
        // Set to default values
        EnetPhy_initCfg(&phyCfg);
    
        // Configure below based on hardware connections and MDIO setup
        phyCfg.phyAddr = 8;   // Based on address called out in schematic
        phyCfg.phyGroup = 0;  // TODO(dharak): Adjust during testing and read from .yaml eventually
    
        // Auto negotiation
        phyCfg.nwayCaps = ENETPHY_LINK_CAP_ALL;
    
        // Auto MDIX
        phyCfg.mdixEn = true;
    
        // Attempt to bypass hardware strapping via firmware, to be tested
        phyCfg.isStrapped = true;
    
        phyCfg.loopbackEn = false;
        phyCfg.masterMode = false;
    
        phyCfg.extClkSource = false;
    
        linkCfg.speed = ENETPHY_SPEED_100MBIT;
        linkCfg.duplexity = ENETPHY_DUPLEX_FULL;
    
        // Get default MDIO driver configuration from enet driver
        EnetPhy_MdioHandle defaultMdio = EnetPhyMdioDflt_getPhyMdio();
    
        phyHandle = EnetPhy_open(&phyCfg, ENETPHY_MAC_MII_RGMII, &linkCfg, ENETPHY_LINK_CAP_ALL,
                                 defaultMdio, NULL);
    
        if (phyHandle == NULL) {
          retVal = 1;
        }
    
        // TODO(dharak): move MDIO/phy state machine into a timer ISR (consult figure team)
        while (linkUpStatus == false) {
          EnetPhy_tick(phyHandle);
          linkUpStatus = EnetPhy_isLinked(phyHandle);
          os_.delay(std::chrono::milliseconds(10U));
        };
    
        EnetPhyMdioDflt_ioctl(phyHandle, ENET_PHY_IOCTL_IS_ALIVE, NULL);
    
        retVal = 1;
    
        return retVal;
      }

    The above code executes without any errors and all functions return ENET_SOK. What we are attempting to do here is:
    1. We have strapped the PHY, via hardware, to be set as a slave

    2. On startup, through a config file or some function input argument, we want to re-configure the PHY to be either a master or slave, regardless of how it is strapped in hardware. We have confirmed this is possible through testing with the TI USB2MDIO tool and a development board which contains our PHY chip.

    So far we are seeing what looks like the internal PHY driver constantly loop through it's internal state machine and keep attempting to find open connections (2 IDs are found to exist).

    Do you have any recommendations on how to proceed? Do we need to disable the state machine before attempting to configure the master/slave register? What mode does the PHY need to be in for us to manage configuration settings? Are the master/slave registers apart of the extended register base C45 or the default C22 base (register 0x0834 is what we need to modify).

    Let me know if you have any questions. I am available to hop on a call at any time of day and would love to show you our debug setup in real time.

    Thanks.

  • Hi Dharak,

    Thanks for clearing up my doubts about the PHY being used with CPSW.

    Q. Do you have the PHY driver files for the DP83TC81x PHY being used?

    Just incase not, you can refer: github.com/.../src

    Do you have any recommendations on how to proceed

    I will share the steps below to help you out. Let's divide this into two parts. PHY driver integration and custom board config

    1. PHY INTEGRATION:

    You will have to add the DP83TC81x PHY header and C files to the enet/core/include/phy and the enet/core/src/phy/ folders.

    Follow the guide at: https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/latest/exports/docs/api_guide_am263x/enetphy_guide_top.html#enetphy_guide_implementing.

    Note: Once you add the files, in makefile.cpsw.am263x.r5f.ti-arm-clang, add the dp83tc812.c file in the list of C files to be compiled and rebuild the enet_cpsw library

    This will have a EnetPhy_Drv structure which will contain a pointer to the config function of the PHY,

    # To clean the library
    gmake -s -f makefile.am263x enet-cpsw_r5f.ti-arm-clang_clean
    
    # To rebuild the library
    gmake -s -f makefile.am263x enet-cpsw_r5f.ti-arm-clang
    

    Once your PHY driver is integrated, you need to modify the Config function in your PHY driver file (for example: Dp83tc812_config()) for writing 14th Bit of the MMD1_PMA_CTRL_2 Register (Address 0x1834) to change mode).

    2. CUSTOM BOARD CONFIG:

    For custom board support please refer: software-dl.ti.com/.../enet_migration_guide_top.html

    Set the board as "custom board" in syscfg. This will allow you to integrate and use custom board config, so generic configuration are not used and you can toggle the state on startup to Master/Slave mode. Enabling “Custom Board” will prevent auto generation of board specific code.

    You will have to write a 'C' file  that is specific to the board. You can refer the following example file from the SDK : C:\ti\mcu_plus_sdk_am263x_09_01_00_41\examples\networking\enet_layer2_multi_channel\am263x-cc\r5fss0-0_freertos\enet_custom_board_config.c

    Then, you will have to extern the EnetPhy_Drv  structure in this custom board config C file as mentioned in the guide.

    Please follow both the guides shared from the SDK documentation thoroughly.

    Do you have any recommendations on how to proceed? Do we need to disable the state machine before attempting to configure the master/slave register? What mode does the PHY need to be in for us to manage configuration settings?

    I believe disabling PHY state machine is not required. You will mostly manipulate your PHY register using the config function. So, after a soft reset is completed and config function for the PHY is called, you can change the mode from Slave to Master.

    The DP83TC81 data sheet mentions the register address and bit to be written to toggle the mode:

    If you refer the PHY State machine diagram, after the PHY is soft-reset, it will transition into ENABLED state. "EnetPhy_enableState()" from enetphy.c will be called, which will check if the extended config is not NULL and skipExtendedCfg is set to false in your custom board config file (Refer point-2). This will then call your PHY drivers config function which should change the state.

    Regards,
    Shaunak

  • Hello,

    We are able to read/write from the registers on both of our DP83TC812 chips, but we are not seeing the master/slave configuration change. Here are the steps we are following, as outlined in document SNLA389 section 3 "Software Configuration".

    We are following this guide as multiple TI E2E posts have said it solved their issues and that the DP83TC812 reference sheet has incorrect register addresses:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1318207/dp83tc812evm-mc-software-configure-master-slave

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1196009/dp83tc812s-q1-phy-link-state-doesn-t-change

    This is the algorithm being used to try and change the master/slave configuration:

    1. Write register 0x18B with value 0xFFFF (to disable autonomous mode)

    2. Write register 0x1F with value 0x8000 (hard reset)

    3. Write register 0x523 with value 0x1 (disable link-up)

    4. Write register 0x0834 with value 0xC000 (for master) or 0x8000 (for slave). We are writing to 0x0834 instead of 0x1834 as settings inside of 0x1834 do not persist, but inside 0x0834 do persist and change the value of 0x1834 as well.

    5. Read register 0x1834 to confirm master/slave config was set. We are reading 0x1834 instead of 0x0834 because they are the same value, but the datasheet calls out 0x1834 for master/slave config.

    6. Write register 0x523 with value 0x0 (re-enable link-up)

    7. Write register 0x18B with value 0x0 (to enable autonomous mode)

    I have tried a vast combination of these registers, including only setting the master/slave config, removing the manual/autonomous mode writes, and writing to 0x1834 and 0x0834 at the same time. I can see the link go down when I do a soft/hard reset or disable link-up, so I know I am writing/reading from the correct PHY. However, when I set my T1 media converter (1000BASET1-MC-ETH from Mach Systems) to slave mode, I do not see my PHY connection LEDs light up, regardless of whether they are in master/slave.

  • Hey Dharak,

    Thank you for posting in detail your latest debug and testing steps!

    As I mentioned over email, I will continue to escalate this internally to get you support ASAP. Thank you for your patience!

    -Matt

  • FYI - This has escalated to offline discussion