AM2632: Purpose of STC Library/test focus of STC

Hi Josef,

The STC stands for CPU self-test controller. It is used to test the CPU core using the deterministic Logic Built-in Self-Test (LBIST) Controller as the test engine. This logic provides a very high diagnostic coverage on the lockstep CPUs. 

All the logics inside the CPU are tested. As the MPU is internal to the CPU core, the LBIST STC diagnostic provides a check of the MPU too.

The test microcode and golden signature value are stored in ROM.

HI Mr. Wang,

thanks for your information. I think we should consider, to use STC also in our functional safety concept.

We use a special bootflow in our AM2632-system (in lockstep mode), because we do pBIST execution for R5SS0 memories from the R5SS1.

Here our flow in words:

The SBL loads and starts R5SS1 firmware and goes into WFI-mode. (R5SS0 firmware is not started from the SBL!!!)
The firmware on R5SS1 executes PBIST for R5SS0 then.
After sucessful pBIST test of the R5SS0 areas, the R5SS1 loads and starts firmware on R5SS0 cluster then.

Here a picture of our flow:

Now I tried to execute the STC example from SDK on the R5SS0 cluster, after this firmware is started from the R5SS1.

I get an error:

STC Test Application started.
If STC test is successfull, Core0 will go in to Reset.
Core0 is Reset.
STC Test is Completed & failing.

Now I tried the same STC example in the same firmware, but now I have changed my SBL. SBL startes directly R5SS0 core. Then I don't get this error.

What can be the reason for this behaviour? (I need the special bootflow, I is no solution, to start R5SS from SBL...)

Thanks and best regards

Josef

Hi Josef,

Can you share your code of loading and starting code execution on R5SS0 from R5SS1?

Hi Mr. Wang,

I do the following steps in my system:

step 1 in the SBL on R5SS0: start the firmware of R5SS1 with this code and enter WFI mode then

/*
 * try to start firmware of R5SS1 from flash
 */
void firmwareStart(void)
{
    int32_t status;
    Bootloader_BootImageInfo bootImageInfo;
    Bootloader_Params bootParams;
    Bootloader_Handle bootHandle;

    Bootloader_Params_init(&bootParams);
    Bootloader_BootImageInfo_init(&bootImageInfo);

    bootHandle = Bootloader_open(CONFIG_BOOTLOADER0, &bootParams);
    if(bootHandle != NULL)
    {
        status = Bootloader_parseMultiCoreAppImage(bootHandle, &bootImageInfo);
        /* Load R5SS1 CPU which will load the R5SS0 after done pBIST/memory test */
        if ((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
        {
            bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_0);
            Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_0);
            status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
        }

        Bootloader_profileAddProfilePoint("CPU load");
        Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle));
        QSPI_Handle qspiHandle = QSPI_getHandle(CONFIG_QSPI0);
        Bootloader_profileUpdateMediaAndClk(BOOTLOADER_MEDIA_FLASH, QSPI_getInputClk(qspiHandle));

        if(status == SystemP_SUCCESS)
        {
            Bootloader_profileAddProfilePoint("SBL End");
            Bootloader_profilePrintProfileLog();
            DebugP_log("Image loading done, switching to application ...\r\n");
            UART_flushTxFifo(gUartHandle[CONFIG_UART0]);
        }

        /* Run R5SS1 CPU */
        if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0)))
        {
            status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]);
        }

        // enter the WFI mode to wait to be booted from R5SS1 CPU
        // disable interrupt first
        HwiP_disableInt(CSLR_R5FSS0_CORE0_INTR_RTI0_INTR_0);
        // enter WFI now
        __asm__ __volatile__ ("wfi"   "\n\t": : : "memory");

        /* it should not return here, if it does, then there was some error */
        Bootloader_close(bootHandle);
    }
}

step 2 is in the R5SS1: the firmware of R5SS1 loads and starts the firmware of R5SS0

/*
 * try to start firmware of master CPU (R5SS0) from flash
 */
void firmwareStartMasterCpu(void)
{
    int32_t status;
    Bootloader_BootImageInfo bootImageInfo;
    Bootloader_Params bootParams;
    Bootloader_Handle bootHandle;

    Bootloader_Params_init(&bootParams);
    Bootloader_BootImageInfo_init(&bootImageInfo);

    bootHandle = Bootloader_open(CONFIG_BOOTLOADER0, &bootParams);
    if(bootHandle != NULL)
    {
        status = Bootloader_parseMultiCoreAppImage(bootHandle, &bootImageInfo);
        /* Load firmware to R5SS0 */
        if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0)))
        {
            bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_0);
            Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_0);
            /* Skip the image load by passing TRUE, so that image load on self core doesnt corrupt the SBLs IVT. Load the image later before the reset release of the self core  */
            status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0]);
        }
        Bootloader_profileAddProfilePoint("CPU load");
        Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle));
        QSPI_Handle qspiHandle = QSPI_getHandle(CONFIG_QSPI0);
        Bootloader_profileUpdateMediaAndClk(BOOTLOADER_MEDIA_FLASH, QSPI_getInputClk(qspiHandle));

        if(status == SystemP_SUCCESS)
        {
            Bootloader_profileAddProfilePoint("SBL End");
            Bootloader_profilePrintProfileLog();
            DebugP_log("Image loading done, switching to application ...\r\n");
            UART_flushTxFifo(gUartHandle[CONFIG_UART0]);
        }

        /* try to run firmware on  R5SS0 */
        if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0)))
        {
            status = Bootloader_runSelfCpu(bootHandle, &bootImageInfo);
        }

        Bootloader_close(bootHandle);
    }
}

I had to change to file bootloader_soc.c/table Bootloader_CoreAddrTranslateInfo gAddrTranslateInfo[]  in the SDK/bootloader-library for my R5SS1-firmware, that R5SS1 loads the R5SS0 firmware to the correct memory adresses (on the right is the new code, used in my R5SS1 firmware).

Regards
Josef

Thanks Josef. I will review the code.

Hi Mr. Wang,

I have some interessting news concerning my problems with the failing STC tests in my special constellation.
The problem is not caused by my bootflow constellation (SBL executes pBIST for R5SS1 and load/run R5SS1 then, R5SS1 executes pBIST for R5SS0 and loads/runs R5SS0 then).

I found out, that STC always fails, when pBIST was executed, before I execute STC...in the next step I tried to further narrow down the problem.
I thought, the problem may be caused by the memory content destruction of the pBIST....so I reduced the memory areas, tested by pBIST step by step...

But the result was, that the memory destruction is no problem for STC...in my last test I disabled all pBIST tests with memory destruction and executed pBIST negative test  

The problem was still existing...so I looked some more deeper into the source files of the pBIST library.

pBIST execution (also the negative tests) enable pBIST engine with a library function SDL_MSS_enableTopPbist. (file sdl_ip_pbist.c)

This function enables the writing to the pBIST registers, by setting the correct key and by bringing pBIST controller out of reset.

After every pBIST test, the function SDL_MSS_disableTopPbist is called, which sould disable the pBIST controller.

I found out,that the disable function does not clear the key, which is entered at the enable function.
I changed the disable-function locally in that way, that the disable-function clears the key from now.

Here my changes of the file sdl_ip_pbist.c (the right side is with my changes).

Now I noticed, that the STC is executed sucessfully.

Is this a bug in the SDL file sdl_ip_bist.c?
Can you confirm this bug?

Thanks and best regards
Jo

Hi Mr. Wang, are there some news for this problems? Can you confirm my reported bug, written in my last message? Best regards, Jo

Hi Jo,

Apologies for late response. My code got stuck when running code in CPU2. I am debugging my code, and try to make it work today. 

Hi Mr. Wang,

can you confirm my reported bug (posted 2months ago, see above), in file sdl_ip_pbist.c?
I am still waiting for your information. 

Best regards,
Jo Scho