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AM2634: Please let me know the reason of the exception during Flash read

YoonJin Kim
Prodigy 110 points
Part Number: AM2634

Hi,

We are using AM2634 MCU and MCAL 9.1.0 version.

Please let me know why exception is occurred at D cache enabled.

If only I cache enabled, there is no exception and working normally. But once enabling I cache and D cache, exception is occurred.

  • 0
    TI__Mastermind 26145 points

    Hi YoonJin Kim,

    The peripheral address space should always be configured as Strongly Ordered to ensure maximum safety during the access of peripheral registers. This may impact the write speeds.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    Prodigy 110 points

    Hi, Kedia,

    In the AM2634 TR documentation, such as Table is existing.

    Region Name Start Address End Address Size
    Core-specific Internal Memory Map 0x0000 0000 0x1FFF FFFF 512MB
    MCRC0 0x3500 0000 0x3500 03FF 1KB
    MPU_L2OCRAM_BANK0 0x4002 0000 0x4002 0FFF 4KB
    ... ... ... ...
    EXT_FLASH0 0x6000 0000 0x61FF FFFF 32MB
    EXT_FLASH1 0x6200 0000 0x63FF FFFF 32MB
    GPMC0_MEM 0x6800 0000 0x6FFF FFFF 128MB
    L2OCRAM 0x7000 0000 0x701F FFFF 2MB
    MBOX_SRAM 0x7200 0000 0x7200 3FFF 16KB

    Can you explain the which area is Peripheral space should I set?

    from 0x3500 0000 to 0x6FFF FFFF, is this region should be set Strongly Ordered?

    -

    And how about ATCM area? is this area to be set to Outer and Inner Non-cacheable?

    R5SS0_CORE0_TCMA_ROM 0x0000 0000 0x0001 FFFF 128K
    R5SS0_CORE0_TCMA_RAM 0x0002 0000 0x0002 FFFF 64KB
  • 0 in reply to YoonJin Kim
    TI__Mastermind 26145 points

    Hi ,

    YoonJin Kim said:
    And how about ATCM area? is this area to be set to Outer and Inner Non-cacheable?

    This is what ARM documentation mentions about TCM MPU settings -

     

    YoonJin Kim said:
    from 0x3500 0000 to 0x6FFF FFFF, is this region should be set Strongly Ordered?

    This is good or you can keep the entire 2GB to set as Strongly Ordered and set the settings of cacheable for RAM etc in the subsequent regions.

    I hope this helps.

    Best Regards,
    Aakash