• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 284 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634: clarification on erata i2355: CONTROLSS-ADC: DMA Read of Stale Result

Prasad Konnur
Prodigy 10 points
Part Number: AM2634

Hi,

As per the am263 errata document, the DMA could read stale result from ADC in some conditions.

Want to confirm if the ADCCTL2 [PRESCALE] is set to 0, DMA would read the proper ADC result value always?

Regards,

Prasad

  • 0
    TI__Mastermind 22953 points

    Hello Prasad,

    The maximum operating frequency of ADCCLK is 50 MHz, since this is operating off SysClock scaled down by the "PRESCALE" value. Since SysClock is 200 MHz, setting PRESCALE to 0 results in a 200 MHz ADCCLK which is an invalid configuration and will result in failure of the ADC module.

    Best Regards,

    Zackary Fleenor