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DCAN SWR bit and Parity RAM

Pashan None
Genius 5660 points

Hello,

If I understand correctly, PBIST will initialize DCAN RAM provided INIT bit = 1 and PMD=0x0A within DCANCTL Register.

After PBIST initializes DCAN RAM Parity area, if I trigger SWR bit of DCANCTL to reset DCAN Peripheral, will it destroy the DCAN RAM PArity contents?

I am assuming SWR bit will alter PMD to 0x05.

I am trying to understand if SWR based DCAN Reset will be disturbing DCAN RAM Parity Area.

Please help me with as much info as possible.

Thank you.

Regards

Pashan

 

  • 0
    TI__Intellectual 1350 points

    Hello Pashan,

    for initialization of the DCAN RAM the Memory Hardware Initialization feature of the system module is used. The SWR bit of the DCAN module should not change the contents of the DCAN RAM. However, as you say, it will set PMD to 0x5, so you need to re-enable parity generation and checking afterwards.

    Best regards

    Andreas

     

  • 0 in reply to Andreas Knickenberg
    TI__Genius 14205 points

    Hi Pashan

    Adding to Andreas comments..

    PBIST is a memory BIST test and this is completely different from Memory Hardware Initialization.

    If running PBIST test on DCAN, PBIST directly targets the DCAN memory and does not disturb any of DCAN module registers. Ofcourse the RAM contents will be lost and application should make sure necessary RAM contents are initialized/filled properly before actually reinitiating for communication.

    Best Regards
    Prathap