TM4C123GH6PM: Request for help on configuring TM4C123G SSI1 Slave

Rahul Mhatre

Part Number: TM4C123GH6PM

Hello,

I am using Keil uvision4 for programming. I have independently verified that SSI1 works fine as a SPI master. Next, I am trying to configure SSI1 of TM4C123G as a SPI slave device. My objective is to read in incoming SPI command value and then transmit a data based of the command value registered. The hardware connections is as shown in picture. SSI3 of first TM4C123G is the SPI master and is transmitting a command value of 0XDC. The master works fine as can be seein in the attached scope plot validating SSI3 funcationality as the SPI master.
Next I configured the SSI1 as slave on the second TM4C123G to register the incoming command 0xDC in a variable. I am having an issue where the SSI1 configured as slave doesn't register the incoming SPI transaction. It seems that the problem may exist either in initializing the GPIO pins (Port F) or configuring SPI1 slave, but I cannot isolate the problem and hence am requesting help to see whether the issue could be identified. I have tried several alternative approaches to configure the SSI1 port as a slave, one instance being forcing SSI1FSS, SSI1CLK, and SSI1Rx as digital inputs and SSI1Tx as digital output, to no avail. The code description is as below. Please let me know as per convenience if any further information is needed.

//Main C File
#include <math.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>

#include "..//tm4c123gh6pm.h"
#include "SSI1.h" //Contains SSI1_Init() and receive8_SSI1() functions
#include "PLL.h"
#include "Timers.h"
#include "UART1.h"
#include "utils/uartstdio.h"
#include "driverlib/fpu.h"
#include "driverlib/uart.h"

void EnableInterrupts(void); // Enable interrupts

uint16_t command;
uint32_t ssi1_rxdata;
unsigned long Flag; // Post Box flag

int main(void){
volatile unsigned long delay;

PLL_Init();
UART1_Init();
SSI1_Init(); // initialize SPI1 as a Slave.
Timer2A_Init(160000);

// Enable lazy stacking for interrupt handlers. This allows floating-point
// instructions to be used within interrupt handlers, but at the expense of
// extra stack usage.
FPUEnable();
FPULazyStackingEnable();

EnableInterrupts();

while(1){
command=receive16_SSI1(); //Register incoming command 0x00DC in a a variable
Flag=0;
// ms_delay(125);
}
}

void SSI1_Init(void){
volatile unsigned long delay;
// SYSCTL_RCGC1_R |= SYSCTL_RCGC1_SSI1; // activate SSI1
SYSCTL_RCGCSSI_R |= 0x02; // activate SSI1
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOF; // activate port F
delay = SYSCTL_RCGC2_R; // allow time to finish activating

GPIO_PORTF_LOCK_R = 0x4C4F434B; // unlock GPIO Port F.
GPIO_PORTF_CR_R |= 0x0F; // allow changes to PF3-0

GPIO_PORTF_AFSEL_R |= 0X0F; // enable alt funct on PF2,1,0, use 0x7 for slave
GPIO_PORTF_PUR_R |= 0x0C; // enable pull-up on PF3,2
GPIO_PORTF_DEN_R |= 0x0F; // enable digital I/O on PF0-3
// configure PF3,2,0 as SSI
GPIO_PORTF_PCTL_R = (GPIO_PORTF_PCTL_R&0xFFFF0000)+0x00002222; //SSI1 is used as slave
GPIO_PORTF_AMSEL_R &= ~0x0F; // disable analog functionality on PF3,2,1,0
// GPIO_PORTF_DIR_R |= 0x08; //make PF3 out (!CS1 signal)
// GPIO_PORTF_DIR_R &= ~0x08; //make PF3 input (!CS1 signal)

SSI1_CR1_R &= ~SSI_CR1_SSE; // disable SSI
// SSI1_CR1_R &= ~SSI_CR1_MS; // master mode
SSI1_CR1_R |= SSI_CR1_MS; // slave mode
// configure for system clock/PLL baud clock source
SSI1_CC_R = (SSI1_CC_R&~SSI_CC_CS_M)+SSI_CC_CS_SYSPLL;
// clock divider for 10 MHz SSIClk (80 MHz PLL/8)
// SysClk/(CPSDVSR*(1+SCR))
// 80/(8*(1+0)) = 10 MHz (faster than 4 MHz)
SSI1_CPSR_R = (SSI1_CPSR_R&~SSI_CPSR_CPSDVSR_M)+8; // must be even number, 10Mhz SPI
SSI1_CR0_R &= ~(SSI_CR0_SCR_M); // SCR = 0 (10 Mbps data rate)
SSI1_CR0_R |= (SSI_CR0_SPH | // SPH = 1
SSI_CR0_SPO); // SPO = 1
// FRF = Freescale format
SSI1_CR0_R = (SSI1_CR0_R&~SSI_CR0_FRF_M)+SSI_CR0_FRF_MOTO;
// DSS = 16-bit data
SSI1_CR0_R = (SSI1_CR0_R&~SSI_CR0_DSS_M)+SSI_CR0_DSS_16;
SSI1_CR1_R |= SSI_CR1_SSE; // enable SSI
}