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AM2431: AM2431 GPMC BE[3:0]_N pins assert low for synchronous single read accesses.

Masanori Sato
Prodigy 20 points
Part Number: AM2431

GPMC0_BE[3:0]_N pin does not work as expected during single read transfer. Single write transfer is no problem. GPMC is used with address data multiplexed and DEVICESIZE=32 bit.

What is wrong with my steps or settings?

Single read access:
(1) Access 0x50200000 with ldrb: GPMC_BE[3:0]_N == 4'b0000. Expected value is 4'b1110.
(2) Access 0x50200000 with ldrh: GPMC_BE[3:0]_N == 4'b0000. Expected value is 4'b1100.
(3) Access 0x50200000 with ldr: GPMC_BE[3:0]_N == 4'b0000

Single write access:
(4) Access 0x50200000 with strb: GPMC_BE[3:0]_N == 4'b1110
(5) Access 0x50200000 with strh: GPMC_BE[3:0]_N == 4'b1100
(6) Access 0x50200000 with str: GPMC_BE[3:0]_N == 4'b0000

The GPMC register settings are below. 

/* CONFIG1_0(NOR Memory Type) */

#define CSL_GPMC_CONFIG1_0_NOR_MEM_TYPE_RESETVAL    (0x28002200U)

 

/* CONFIG7_0(NOR CS Configuration) */

#define CSL_GPMC_CONFIG7_0_NOR_CS_CONFIG_RESETVAL   (0x00000E10U)

 

/* CONFIG1_0(WAIT Pin Configuration) */

#define CSL_GPMC_CONFIG1_0_WAIT_PIN_CONFIG_RESETVAL (0x00600000U)

 

/* CONFIG(WAIT Pin Configuration) */

#define CSL_GPMC_CONFIG_WAIT_PIN_CONFIG_RESETVAL    (0x00000100U)

 

/* CONFIG1_0(Timing parameters) */

#define CSL_GPMC_CONFIG1_0_TIMING_PARAMS_RESETVAL   (0x28000200U)

 

/* CONFIG2_0(Timing parameters) */

#define CSL_GPMC_CONFIG2_0_TIMING_PARAMS_RESETVAL   (0x00050581U)

 

/* CONFIG3_0(Timing parameters) */

#define CSL_GPMC_CONFIG3_0_TIMING_PARAMS_RESETVAL   (0x22040415U)

 

/* CONFIG4_0(Timing parameters) */

#define CSL_GPMC_CONFIG4_0_TIMING_PARAMS_RESETVAL   (0x05804592U)

 

/* CONFIG5_0(Timing parameters) */

#define CSL_GPMC_CONFIG5_0_TIMING_PARAMS_RESETVAL   (0x00040505U)

 

/* CONFIG6_0(Timing parameters) */

#define CSL_GPMC_CONFIG6_0_TIMING_PARAMS_RESETVAL   (0x04020000U)

 

/* CONFIG7_0(Enable CS) */

#define CSL_GPMC_CONFIG7_0_ENABLE_CS_RESETVAL       (0x00000040U)
  • 0
    TI__Mastermind 47046 points

    Hello ,

    I am looking at your queries and you may expect reply by today .

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    TI__Mastermind 47046 points

    Hello ,

    Can you please share the below details to further debug the issue ?

    1. Please share the Part number or datasheet for which device is connected to AM243?

    2. I assume that the above write and read operations you are doing code in assembly.

    So, please share the write and read code snippet to better understand.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Prodigy 20 points

    Hi S.Anil,

    Thank you for your consideration.

    1. An FPGA with a GPMC interface is connected. The timing chart for single read and single write is shown below.

    gpmc-single-readgpmc-single-write

    2. The read and write code snippet is shown below.gpmc-single-read-code

    gpmc-single-write-code

    GPMC_CONFIGn_i register settings are also shared.

    (R)address:3B000060 = 28602200
    (R)address:3B000064 = 00050581
    (R)address:3B000068 = 22040415
    (R)address:3B00006C = 05804592
    (R)address:3B000070 = 01040505
    (R)address:3B000074 = 84020000
    (R)address:3B000078 = 00000e50

    Regards,
    Masanori Sato

  • 0 in reply to Masanori Sato
    TI__Mastermind 47046 points

    Hello Masanori Sato,

    In the NOR or PSRAM memory there is just the memcopy operation and no need to send any commands for the read and write operation.

    From GPMC to you have connected to FPGA. So, in FPGA I am assumed that, based on this signal (BE), you are trying to transfer 32bit only.

    So, I am just wondering in the read mode whether the FPGA is sending the data or not.

    Can you please confirm whether data is sent by the GPMC or not ?

    If data is sent by the FPGA that is not able to read at the GPMC peripheral side, then check your MPU settings properly configured to CS region or not.

    Actually, on AM263 we have PSRAM 16 a bit example, you can refer to them for your case of use.

    And one more thing is that I hope you are using only one pin BE signal and one CS line.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Prodigy 20 points

    Hi Swargam Anil

    It used STRB(8 bit) / STRH(16 bit) / STR(32 bit) for write operations and GPMC0_BE[3:0]_N pins asserted or non-asserted according to system requirements.
    It used LDRB(8 bit) / LDRH(16 bit) / LDR(32 bit) for read operations and GPMC0_BE[3:0]_N pins were all asserted regardless of system requirements.
    We confirmed these codes are running, using XDS110 and TI CCS.

    Data is being transferred by the GPMC. Except for the operation of GPMC0_BE[3:0]_N pins during single read, data can be written and read.
    The waveforms of monitored FPGA internal signals are shown below.

    STRB (CPU register to GPMC)
    Address: 50000000h, Data: 78h


    Address: 50000003h, Data: 78


    LDRB (GPMC to CPU register)
    Address: 50000000h

    Address: 50000003h


    In TI's lab, when DEVICESIZE=2h (32 bit), READMULTIPLE=0h (Single access), READTYPE=1h (Read synchronous), GPMC0_BE[3:0]_N pins are asserted or GPMC0_BE[3:0]_N pins assert or non-assert according to the system requirements? What are the values of GPMC_CONFIG1-7?

    Regards,
    Masanori Sato

  • 0 in reply to Masanori Sato
    TI__Mastermind 47046 points

    Hello Masanori Sato,

    Actually, I don't have AM263X HW with me and don't support on this device , and I can try to get this configuration.

    I assume that this bit can't be controlled by GPMC in 32-bit mode.

    FYI,GPMC-BE0 belongs to CS0, and GPMC_BE1 belongs to CS1, CS2 for BE2, and CS3 for BE3.

    Even when you write an 8-bit value in the CS address in 32-bit mode, GPMC will try to send 32-bit only.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Prodigy 20 points

    Hi Swargam Anil,

    I'm using AM2431. If you try it, please use AM243X HW.

    > I assume that this bit can't be controlled by GPMC in 32-bit mode.
    Does this mean that the Byte Enable pins cannot be controlled in a single read transfer?
    It would be helpful if you could show me the evidence.
    12.3.3.4.7.3.5 Byte Enable in SPRUIM2H has the following description. It seems to control the Byte Enable pins for single transfer regardless of Read/Write.
    ---
    www.ti.com/.../spruim2h.pdf
    12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
    Byte enable signals (nBE1/nBE0) are:
    • Valid (asserted or nonasserted according to the incoming system request) from access start to access completion for asynchronous and synchronous single accesses
    ---

    >FYI,GPMC-BE0 belongs to CS0, and GPMC_BE1 belongs to CS1, CS2 for BE2, and CS3 for BE3.
    My understanding is that GPMC0_BE0n_CLE and GPMC0_BE[3-1]n do not belong to any particular CSn. Figure 12-1609 "GPMC to 32-Bit Address/Data-Multiplexed Memory" in SPRUIM2H states that it can be used with GPMC0_CSni (i=0 to 3).

    Regards,
    Masanori Sato

  • 0 in reply to Masanori Sato
    Prodigy 20 points

    Hello Swargam Anil,

     

    I am reaching out to inquire about any updates or progress on the operation of the AM2431’s GPMC in 32-bit mode.  Specifically, I would like to confirm whether it is standard behavior for all GPMC0_BE0n_CLE and GPMC0_BE[3-1]n signals to assert during a synchronous single read transfer in this mode. Is this consistent with the device specifications?

     

    Thank you for your assistance and I look forward to your prompt response.

     

    Best regards,

     

    Masanori Sato