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RM46L852: SPI in slave mode sets DMA RX PEND-bit when SPI is disabled if DMAREQEN is enabled

Jarkko Silvasti
Expert 1395 points
Part Number: RM46L852
Other Parts Discussed in Thread: HALCOGEN

Hello,


I made following observation the SPI signals; "bogus" PEND-bit is set to DMA if SPI is used in slave mode and you disable it. Can you confirm? Cannot found any remarks on such behavior from the reference manual...

This is very trivial to try, just need to configure the DMA to be interested on SPI requests (not showing that part)

In slave mode:
// config DMA to listen requests from SPI

ptSpi->GCR1 = 0U; // disable & slave mode
ptSpi->INT0 = 0U; // remove what ever HALCoGen has set
ptSpi->INT0 |= SPI_INT0_DMAREQEN;  // enable DMA
ptSpi->GCR1 |= SPI_GCR1_EN; // enable SPI -> this creates PEND for TX (as supposed to)
ptSpi->GCR1 &= (uint32)~SPI_GCR1_EN; // shut off SPI -> This creates PEND for RX channel!!!

In master mode it works correctly:
// config DMA to listen requests from SPI

ptSpi->GCR1 = 0U; // disable & slave mode
ptSpi->GCR1 |= SPI_GCR1_MASTER; // enable master mode
ptSpi->INT0 = 0U; // remove what ever HALCoGen has set
ptSpi->INT0 |= SPI_INT0_DMAREQEN;  // enable DMA
ptSpi->GCR1 |= SPI_GCR1_EN; // enable SPI -> this creates PEND for TX (as supposed to)
ptSpi->GCR1 &= (uint32)~SPI_GCR1_EN; // shut off SPI -> no PEND for RX


In slave mode if removing the DMAREQEN before disable then PEND for RX isn't created
...
ptSpi->INT0 &= ~SPI_INT0_DMAREQEN;  // remove DMA
ptSpi->GCR1 &= (uint32)~SPI_GCR1_EN; // shut off SPI -> no PEND for RX

  • 0
    Expert 1395 points

    I forgot to mention that MIBSPI#137 item covers this one, but I observed the same without this condition (our CS line is in 3v3 state in this case)
    "The nSCS (Chip Select) pin is in active state, but no transfers are active."

    So looks like that the safest way is to always remove the DMAREQEN before the disable?

  • 0 in reply to Jarkko Silvasti
    TI__Guru 69771 points

    Hi Jarkko,

    I started working on your issue, and will provide you an update ASAP.

    --
    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1395 points

    I investigated this further and looks like if all CS bits are zeroed in PC0 register (turned to GIO) only then PEND bit won't get set in SPI disable. DAT1: CSNR value looks to have no effect.

  • 0 in reply to Jarkko Silvasti
    TI__Guru 69771 points

    Hi Jarkko,

    Jarkko Silvasti said:
    I investigated this further and looks like if all CS bits are zeroed in PC0 register (turned to GIO) only then PEND bit won't get set in SPI disable. DAT1: CSNR value looks to have no effect.

    May be you are configuring SPI functionality for all the CS pins in HALCoGen.

    Try to configure SPI functionality for CS0 only and then verify w.r.t CS state:

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1395 points

    As I said above, it does not help. Need to remove all the CS bits from PC0.

    PC0 with value = 0x03030E01 generates PEND
    PC0 with value = 0x03030E00 does not generate PEND

  • 0 in reply to Jarkko Silvasti
    TI__Guru 69771 points

    Hi Jarkko,

    Apologies for the delay in my response.

    Today i tested the behavior you are mentioned on my PC.

    Here is my output when the CS0 functionality enabled and it is connected with GND:

    In above image 0th bit in PC0 represents the CS0 functionality, it is 1 means CS0 functionality is SET to the CS0 not GIO.

    0th bit in PC2 represents the current input value of CS0, as you can see it is 0 (i.e. CS is GND).

    So, in this case DMA CH0 pending bit set, that is we received SPI RX DMA REQ.

    Here is my output when the CS0 functionality enabled and it is connected with 3.3V:

    In this case you can see CS0 functionality SET same as above but CS0 input value is now 1(i.e. CS is 3.3V).

    So, in this case DMA CH0 pending bit reset, that is we didn't receive SPI RX DMA REQ in this case.

    Here is my tested code for your reference:

    SPI_PEND_BIT_ISSUE_RM46.zip

    --
    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1395 points

    I'll believe your results but mine works differently. Could this differ based on CPU this one is RM46L852ZWT.

    Also having oscilloscope in CS0 to catch possible short down signals and scobe do not trigger.

    Starting situation

    And after disable (just wroted the disable bit with debugger)


    If I remove the CS from PC0

    And then make disable the PEND it not set

  • 0 in reply to Jarkko Silvasti
    TI__Guru 69771 points

    Hi Jarkko,

    It was strange.

    Jarkko Silvasti said:
    Could this differ based on CPU this one is RM46L852ZWT.

    Mostly it should not be the issue. 

    Which board you are using? Is it a custom board? Is your schematic sharable?

    Can you please share your complete project?

    --
    Thanks & Regards,
    Jagadish.