MSPM0L1306: Priority change inside group interrupts and outside group interrupts

Wayne Huang

Genius 16325 points

Part Number: MSPM0L1306

Dear Champs,

I am asking this for our customer.

The user is aware there are up to 32 IRQx for Cortex M0 and there are 4 different priorities.

But for group interrupts, the uses is concerned about how to adjust its priorities.

For example , like GROUP1 below,

1. Is it possible to make COMP0 in lower priority than GPIO0?

2. Is it possible to make COMP0 in lower priority than TIMG0, and at the same time GPIO0 higher than TIMG0?

3. Is it possible to make COMP0 in higher priority than TIMG0, and at the same time GPIO0 lower than TIMG0?

0 Helic Chi over 1 year ago

You can manually read COMP0 and GPIO0's CPU_INT MIS register.

Manually manage every set interrupt, and manually clear interrupt flag by writing ICLR register.

One by one in interrupt IRQ.

You can firstly read the description of CPU_INT register including IIDX, IMASK, RIS, MIS, ISET, ICLR.

In TRM, peripheral's register chapter.

8.3

Regards,

Helic

0 Wayne Huang over 1 year ago in reply to Helic Chi

Dear Helic,

I am still confused.

It makes sense to use MIS to solve question 1.

But for question 2 and 3, how does the user make the same IRQ1 (GROUP1) higher and lower than IRQ16 (TIMG0) simultaneously?

+1 Helic Chi over 1 year ago in reply to Wayne Huang

For question 2 and 3: No.

M0 can not set different priority interrupt in same group separately.

Regards,

Helic

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