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MSPM0G3107: How to properly restart a basic timer in one -shot down counting mode

Mykola Zaitsev
Prodigy 70 points
Part Number: MSPM0G3107

Hello,

I have a question on how to restart a basic timer correctly (I have ran into weird behavior).

If I configure Timer A  in "One-shot Down Counting" mode and enable "Zero event" interrupt to get

a callback every time it expires, should I manually stop the counter before restarting the timer ?

So basically which one of the two is correct ?

Option 1:

DL_TimerA_stopCounter(TIMER_0_INST);

DL_TimerA_setLoadValue(TIMER_0_INST, timeout_ms * TIMER_CLK_FREQ_kHz);

DL_TimerA_startCounter(TIMER_0_INST);

Option 2:

DL_TimerA_setLoadValue(TIMER_0_INST, timeout_ms * TIMER_CLK_FREQ_kHz);

DL_TimerA_startCounter(TIMER_0_INST);

Thanks,

Mykola

  • 0
    TI__Mastermind 28070 points

    Hi Mykola,

    You shouldn't need to reload the timer manually. 

    If you are in one-shot, down count mode you should just be able to call DL_TimerA_startCounter and that will set the CTRCTL.EN bit to begin counting from the load value again.

    The only reason to change the load value would be if you wanted a different period for the next Load->Zero timeframe. In that case Option 2 would be correct. 

    Best Regards,
    Brandon Fisher

  • 0
    Prodigy 70 points

    Hi Brandon,

    Thank you for getting back to me. 

    I indeed use it with variable period and reload the value every time before starting the timer again.

    The problem that I ran into is that when I clock the timer from LFCLK I cannot seem to restart it from the IRQ handler unless I add a delay or call DL_TimerA_stopCounter.

    If I clock the peripheral from a faster clock source then it behaves as expected and I do not need to stop it or use any delays. Might be 

  • 0 in reply to Mykola Zaitsev
    Prodigy 70 points

    Might be a problem in my setup, but I am not sure. Curious if you observe the same behavior. 

  • +1 in reply to Mykola Zaitsev
    TI__Mastermind 28070 points

    Hi Mykola,

    I'm checking with design on this, but it looks to me like the CTRCTL.EN bit is still set when the zero interrupt fires here, even though the counter is zero. I suspect that this bit takes a TIMCLK cycle to clear, but with your CPU operating at 32MHz or 80MHz you potentially going to have thousands of MCLK cycles before that TIMCLK occurs. 

    That CTRCTL.EN bit is what DL_TimerA_startCounter is setting. If it is not cleared it has no effect. So calling the stop counter function is appropriate in this case, as your CPU can update that register value faster than the hardware path when* TIMCLK is that much slower.

    Will let you know when I confirm either way if this is the case. 

    Best Regards,
    Brandon Fisher

  • 0 in reply to Brandon Fisher94
    Prodigy 70 points

    Hi Brandon,

    Thank you for looking into this, this makes sense to me.

    Best regards,

    Mykola